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LSM303AGR bảng dữ liệu(PDF) 51 Page - STMicroelectronics |
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LSM303AGR bảng dữ liệu(HTML) 51 Page - STMicroelectronics |
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51 / 68 page  DocID027765 Rev 5 51/68 LSM303AGR Register description 68 8.17 FIFO_CTRL_REG_A (2Eh) 8.18 FIFO_SRC_REG_A (2Fh) Table 55. FIFO_SRC_REG_A description Table 51. FIFO_CTRL_REG_A register FM1 FM0 TR FTH4 FTH3 FTH2 FTH1 FTH0 Table 52. FIFO_CTRL_REG_A description FM[1:0] FIFO mode selection. Default value: 00 (see Table 53) TR Trigger selection. Default value: 0 0: trigger event allows triggering signal on INT1 1: trigger event allows triggering signal on INT2 FTH[4:0] Default value: 00000 Table 53. FIFO mode configuration FM1 FM0 FIFO mode 0 0 Bypass mode 0 1 FIFO mode 1 0 Stream mode 1 1 Stream-to-FIFO mode Table 54. FIFO_SRC_REG_A register WTM OVRN_FIFO EMPTY FSS4 FSS3 FSS2 FSS1 FSS0 WTM WTM bit is set high when FIFO content exceeds watermark level. OVRN_FIFO OVRN bit is set high when FIFO buffer is full; this means that the FIFO buffer contains 32 unread samples. At the following ODR a new sample set replaces the oldest FIFO value. The OVRN bit is set to 0 when the first sample set has been read. EMPTY EMPTY flag is set high when all FIFO samples have been read and FIFO is empty. FSS [4:0] FSS [4:0] field always contains the current number of unread samples stored in the FIFO buffer. When FIFO is enabled, this value increases at ODR frequency until the buffer is full, whereas, it decreases every time one sample set is retrieved from FIFO. |
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