LSM303AGR datasheet(34/68 Pages) STMICROELECTRONICS

34 / 68 page

Application hints

LSM303AGR

34/68

DocID027765 Rev 5

Application hints

Figure 10. LSM303AGR electrical connections

The device core is supplied through the Vdd line while the I/O pads are supplied through the

Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 μF aluminum) should

be placed as near as possible to pin 9 of the device (common design practice).

It is possible to remove Vdd, maintaining Vdd_IO, without blocking the communication bus,

in this condition the measurement chain is powered off.

The following recommendations apply to capacitor C1:



It must be connected as close as possible to pins 5 and 6 since very high current

pulses flow from C1 to pin 5 and 6. This avoid problems caused by inductive effects

due to the length of the copper strips.



It is highly recommended to use low ESR (max 200 mOhm)

The functionality of the device and the measured acceleration data are selectable and

accessible through the I2C or SPI interfaces. When using the I2C, CS must be tied high (i.e.

connected to Vdd_IO).

The functions, the threshold and the timing of the three interrupt pins (INT_1_XL, INT_2_XL,

and INT_MAG) can be completely programmed by the user through the I2C/SPI interface.

5.1

Soldering information

The LGA package is compliant with the ECOPACK®, RoHS and “Green” standards.

It is qualified for soldering heat resistance according to JEDEC J-STD-020.

Leave “Pin 1 Indicator” unconnected during soldering.

Land pattern and soldering recommendations are available at www.st.com.

LSM303AGR bảng dữ liệu(PDF) 34 Page - STMicroelectronics