LSM303AGR datasheet(62/68 Pages) STMICROELECTRONICS

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LSM303AGR

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DocID027765 Rev 5

8.41

CFG_REG_C_M (62h)

Table 97. CFG_REG_C_M register

Table 98. CFG_REG_C_M register description

8.42

INT_CTRL_REG_M (63h)

The interrupt control register is used to enable and to configure the interrupt recognition.

Table 99. INT_CRTL_REG_M register

Table 100. INT_CTRL_REG_M register description

INT_MAG

_PIN

I2C_DIS

BDU

BLE

0(1)

1. This bit must be set to ‘0’ for the correct operation of the device.

Self_test

INT_MAG

INT_MAG_PIN

If '1', the INTERRUPT signal (INT bit inside INT_SOURCE_REG_M (64h)) is

driven on INT_MAG_PIN

I2C_DIS

If ‘1’, the I2C interface is inhibited. Only the SPI interface can be used.

BDU

If enabled, reading of incorrect data is avoided when the user reads asynchro-

nously. In fact if the read request arrives during an update of the output data, a

latch is possible, reading incoherent high and low parts of the same register. Only

one part is updated and the other one remains old.

BLE

If ‘1’, an inversion of the low and high parts of the data occurs.

Self_test

If ‘1’, the self-test is enabled.

INT_MAG

If ‘1’, the DRDY pin is configured as a digital output.

XIEN

YIEN

ZIEN

0(1)

1. This bit must be set to ‘0’ for the correct operation of the device.

0(1)

IEA

IEL

IEN

XIEN

Enables the interrupt recognition for the X-axis. Default: 0

1: enabled; 0: disabled.

YIEN

Enables the interrupt recognition for the Y-axis. Default: 0

1: enabled; 0: disabled.

ZIEN

Enables the interrupt recognition for the Z-axis. Default: 0

1: enabled; 0: disabled.

IEA

Controls the polarity of the INT bit (INT_SOURCE_REG_M (64h)) when an interrupt

occurs. Default: 0

If IEA = 0, then INT = 0 signals an interrupt

If IEA = 1, then INT = 1 signals an interrupt

IEL

Controls whether the INT bit (INT_SOURCE_REG_M (64h)) is latched or pulsed.

Default: 0

If IEL = 0, then INT is pulsed.

If IEL = 1, then INT is latched.

Once latched, INT remains in the same state until INT_SOURCE_REG_M (64h) is read.

IEN

Interrupt enable. When set, enables the interrupt generation. The INT bit

is in INT_SOURCE_REG_M (64h). Default: 0

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