L9779WD datasheet(110/170 Pages) STMICROELECTRONICS

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Functional description

L9779WD

110/170

DocID027452 Rev 5

6.17

Monitoring module (watchdog)

6.17.1

WDA - Watchdog (algorithmic)

Basic feature

Via MSC bus a WDA "question" must be read from a MSC register. A correct response must

be written back via MSC in a well defined timing. If response or timing is not correct, then

the WDA error counter EC is increased. If the error counter is increased to values greater

than 4, some output functions are shut off. If the error counter reaches values greater than 7

(overflow), then a RST reset may be generated if this is previously configured via MSC.

On the other way round, with a RST event also the WDA output pin goes to low.

Note that after startup, reset or an overflow the initial value of the error counter is 6.

If WDA resets are enabled via MSC: The number of RST events generated by an error

counter overflow is limited by the reset counter RST_CNT. If RST_CNT reaches the value of

7, then RST resets via WDA are no longer generated.

In case many WDA events occur during after-run power latch mode, the power latch mode

is terminated by the AB1 counter: With each error counter overflow, the AB1 counter is

increased. If it reaches a value greater than 7, then the after-run power latch mode is

terminated.

Table 49. WDA_INT electrical characteristics

Symbol

Parameter

Test condition

Min

Typ

Max

Unit

WDA_INT

VWDA_low

Output low voltage

3.5 V < VDD5

IWDA < 4 mA

0.4

2.2 V < VDD5 < 3.5V

IWDA < 1 mA

0.4

IWDA

Input leakage current

µA

VWDA_in_low

Input voltage low level

-0.3

1.1

VWDA_in_high Input voltage high level -

2.3

VDD_IO

+0.3

VWDA_in_hys

Input voltage

hysteresis

300

800

Rpullup

Internal pull-up resistor -

150

kΩ

fCLK1

WDA clock CLK1

-5%

kHz

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