SN65DP149 datasheet(9/52 Pages) TI1

9 / 52 page

SN65DP149, SN75DP149

www.ti.com

SLLSEL2A – SEPTEMBER 2015 – REVISED DECEMBER 2015

7.6 Differential Input Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DR_RX_DATA

Ddata lanes data rate

0.25

3.4

Gbps

DR_RX_CLK

Clock lanes clock rate

340

MHz

tRX_DUTY

Input clock duty circle

40%

50%

60%

tCLK_JIT

Input clock jitter tolerance

0.3

Tbit

tDATA_JIT

Input data jitter tolerance

Test the TTP2, see Figure 7

150

Test at TTP2 when DR = 1.6-Gbps, see

TRX_INTRA

Input intra-pair skew tolerance

112

Figure 7

TRX_INTER

Input inter-pair skew tolerance

1.8

Fixed EQ gain for data lane

EQ_SEL/A0 = H; Fixed EQ gain,

EQH(D)

IN_D(0,1,2)n/p

test at 3.4-Gbps

Fixed EQ gain for data lane

EQ_SEL/A0 = L; Fixed EQ gain,

EQL(D)

7.5

IN_D(0,1,2)n/p

test at 3.4-Gbps

Adaptive EQ gain for data lane

EQZ(D)

EQ_SEL/A0 = Z; adaptive EQ

IN_D(0,1,2)n/p

EQ(c)

EQ gain for clock lane IN_CLKn/p

EQ_SEL/A0 = H,L,NC

RINT

Input differential termination impedance

100

120

Ω

VITERM

Input termination voltage

OE = H

0.7

VID_PP

Input differential voltage (peak to peak)

Tested at TTP2, check Figure 7

1200

mVPP

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