SN65DP149 datasheet(39/52 Pages) TI1

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SN65DP149, SN75DP149

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SLLSEL2A – SEPTEMBER 2015 – REVISED DECEMBER 2015

Typical Application (continued)

9.2.1 Design Requirements

The SNx5DP149 can be designed into many types of applications. All applications have certain requirements for

the system to work properly. Two voltage rails are required to support the lowest possible power consumption.

The OE pin must have a 0.1-µF capacitor to ground. This pin can be driven by a processor but the pin needs to

change states after voltage rails have stabilized. Configure the device by using I2C. Pin strapping is provided as

I2C is not available in all cases. Because sources may have different naming conventions, confirm the link

between the source and the SNx5DP149 is correctly mapped. A swap function is provided for the input pins in

case signaling is reversed between the source and the device. For the control pins the values provided below are

when they are being controlled by a micro-controller. If this is not the case then using the 65-k

Ω for a pull up for

high, pulled down for low, and left floating for mid level.

Table 13. Design Parameters

DESIGN PARAMETER

VALUE

VCC

3.3 V

VDD

1.1 V

Main link input voltage

VID = 75 mVpp to 1.2 Vpp

Control pin Low

65-k

Ω pulled to GND

Control pin Mid

No Connect

Control pin High

65-k

Ω pulled to 3.3-V

Vsadj resistor

7.06-k

Ω

Main link AC decoupling capacitor

75 to 200 nF, recommend 100 nF

9.2.2 Detailed Design Procedure

The SNx5DP149 is a signal conditioner that provides AC coupling to DC coupling level shifting, to support Dual

Mode DisplayPort-capable GPUs or GPUs with AC-coupled drive capability to support HDMI or DVI connectors

and compliance. Signal conditioning is accomplished using receive equalization, retiming, and output driver

configurability. The transmitter drives 2 to 3 inches of board trace and connector.

Designing in the SNx5DP149 requires the following:

•

Determine the loss profile between the GPU and the HDMI/DVI connector.

•

Based upon the loss profile and signal swing, determine the optimal location for the SNx5DP149, to pass

electrical compliance.

•

Use the typical application drawings in Use Case of SNx5DP149 for information on using the AC coupling

capacitors and control pin resistors.

•

The DP149 has a receiver adaptive equalizer by default but can also be configured for fixed value

equalization using the EQ_SEL control pin.

•

Set the VOD, pre-emphasis, termination, and edge rate levels to support compliance by using the appropriate

Vsadj resistor value and by setting the PRE_SEL and SLEW_CTL control pins.

•

The thermal pad must be connected to ground.

•

See the schematics in Application Information on recommended decouple capacitors from VCC pins to

ground.

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