SN65DP149 datasheet(32/52 Pages) TI1

32 / 52 page

SN65DP149, SN75DP149

SLLSEL2A – SEPTEMBER 2015 – REVISED DECEMBER 2015

www.ti.com

Table 7. Misc Control (continued)

ADDRESS

BIT

DEFAULT DESCRIPTION

ACCESS

Application Mode Selection

0 – Source (default) - Set the adaptive EQ mid point to between 6.5-dB and 7.5-dB

1’b0

1 – Sink - Sets the adaptive EQ starting point to between 12-dB and 13-dB

HPDSNK_GATE_EN: This field sets the functional relationship between HPD_SNK and

HPD_SRC.

1’b0

0 – HPD_SNK passed through to the HPD_SRC (default)

1 – HPD_SNK will not pass through to the HPD_SRC.

EQ_ADA_EN: this field enables the equalizer working state.

0 – Fixed EQ

1’b1

RWU

1 – Adaptive EQ (default)

Writes are ignored when I2C_EN/PIN = 0

EQ_EN: this field enables the receiver equalizer.

1’b1

0 – EQ disabled

1 – EQ enable (default)

0Ah

1’b0

Reserved

APPLY_RXTX_CHANGES , Self clearing write-only bit. Writing a 1 to this bit will apply new

slew, tx_term, twpst1, eqen, eqadapten, swing, eqftc, eqlev settings to the clock and data

1’b0

lanes. Writes to the respective registers do not take immediate effect. This bit does not need

to be written if I2C configuration occurs while OE or hpd_sink are low, I2C power down is

active.

DEV_FUNC_MODE: This field selects the device working function mode.

00 – Redriver mode across full range 250 Mbps to 3.4-Gbps

01 - Automatic redriver to retimer crossover at 1.0 Gbps (default)

10 - Reserved

1:0

2’b01

11 - Retimer mode across full range 250 Mbps to 3.4-Gbps

When moving between the different modes, the device needs to toggle the power setting

from 1 to 0, then back to 1, for proper initializing of the crossover mode.

Mode Selection Definition: This bit lets the receiver know where the device is located in a system for the

purpose of centering the AEQ point. The SNx5DP149 is targeting the source application, so the default value is

0, which will center the EQ at 6.5 to 7.5-dB , see Table 9. If the SNx5DP149 is in a dock or sink application, the

value should be changed to a value of 1, which will center the EQ at 12 to 13-dB .

8.5.4.2.3

HDMI Control

Table 8. HDMI Control

ADDRESS

BIT

DEFAULT

DESCRIPTION

ACCESS

SLEW_CTL. Slew rate control.2’00 is fastest and 2’b11 is slowest

7:6

2’b00

RWU

Writes ignored when I2C_EN/PIN = 0

HDMI_SEL: Contro; Writes ignored when I2C_EN/PIN = 0l

0 – HDMI (default)

1’b0

RWU

1 – DVI

TX_TERM_CTL: Controls termination for HDMI TX

00 – No termination

0Bh

01 – 150 to 300-

4:3

2’b00

RWU

10 – Reserved

11 - Reserved

1’b0

Reserved

1’b0

. Reserved

1’b0

Reserved

Submit Documentation Feedback

Product Folder Links: SN65DP149 SN75DP149

SN65DP149 bảng dữ liệu(PDF) 32 Page - Texas Instruments

SN65DP149 bảng dữ liệu(HTML) 32 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

bảng dữ liệu tải về

Link URL