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LAN9730 bảng dữ liệu(PDF) 203 Page - Microchip Technology

tên linh kiện LAN9730
Giải thích chi tiết về linh kiện  High-Speed Inter-Chip USB 2.0 to 10/100 Ethernet Controller
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nhà sản xuất  MICROCHIP [Microchip Technology]
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LAN9730 bảng dữ liệu(HTML) 203 Page - Microchip Technology

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 2012-2015 Microchip Technology Inc.
DS00001946A-page 203
LAN9730/LAN9730i
7.5.3
POWER-ON CONFIGURATION STRAP VALID TIMING
Figure 7-3 illustrates the configuration strap valid timing requirement in relation to power-on. In order for valid configu-
ration strap values to be read at power-on, the following timing requirements must be met.
7.5.4
RESET AND CONFIGURATION STRAP TIMING
Figure 7-4 illustrates the nRESET pin timing requirements and its relation to the configuration strap pins and output
drive. Assertion of nRESET is not a requirement. However, if used, it must be asserted for the minimum period specified.
FIGURE 7-3:
POWER-ON CONFIGURATION STRAP VALID TIMING
TABLE 7-15:
POWER-ON CONFIGURATION STRAP VALID TIMING
Symbol
Description
Min.
Typ.
Max.
Unit
tcfg
Configuration strap valid time
15
ms
FIGURE 7-4:
nRESET RESET PIN TIMING
TABLE 7-16:
nRESET RESET PIN TIMING VALUES
Symbol
Description
Min.
Typ.
Max.
Unit
trstia
nRESET input assertion time
1
µs
tcss
Configuration strap pins setup to nRESET deassertion
200
ns
tcsh
Configuration strap pins hold after nRESET deassertion
10
ns
todad
Output drive after nRESET deassertion
30
ns
VDD33IO
Configuration Straps
tcfg
2.0 V
tcss
nRESET
Configuration
Strap Pins
trstia
tcsh
Output Drive
todad



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