LAN8820I datasheet(9/83 Pages) MICROCHIP

9 / 83 page

 2009-2015 Microchip Technology Inc.

DS00001871B-page 9

LAN8820/LAN8820I

TABLE 2-5:

JTAG PINS

Num Pins

Name

Symbol

Buffer

Type

Description

JTAG Test

Data Out

TDO

JTAG (IEEE 1149.1) data output.

JTAG Test

Data Input

TDI

(PU)

JTAG (IEEE 1149.1) data input.

Note:

When not used, tie this pin to VDD25IO.

JTAG Test

Clock

TCK

(PD)

JTAG (IEEE 1149.1) test clock.

Note:

When not used, tie this pin to VSS.

JTAG Test

Mode Select

TMS

(PU)

JTAG (IEEE 1149.1) test mode select.

Note:

When not used, tie this pin to VDD25IO.

TABLE 2-6:

MISCELLANEOUS PINS

Num Pins

Name

Symbol

Buffer

Type

Description

Crystal Input

ICLK

External 25 MHz crystal input.

Note:

This pin can also be driven by a 25 MHz

single-ended clock oscillator. When this

method is used, XO should be left

unconnected. Refer to Section 5.6,

"Clock Circuit," on page 75 for additional

information.

Crystal

Output

OCLK

External 25 MHz crystal output.

System Reset

nRESET

(PU)

This active-low pin allows external hardware to

reset the device.

Interrupt

Request

IRQ

Programmable interrupt request.

Note:

When used, this pin requires an

external 4.7K pull-up resistor.

Hardware

Power Down

HPD

(PD)

When asserted, this pin places the device into

Hardware Power Down (HPD) mode. Refer to

Section 3.7.3, "Hardware Power-Down," on

page 23 for additional information.

No Connect

This pin must be left floating for normal device

operation.

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