LAN8820I datasheet(46/83 Pages) MICROCHIP

46 / 83 page

LAN8820/LAN8820I

DS00001871B-page 46

 2009-2015 Microchip Technology Inc.

4.2.15

10/100 SPECIAL MODES REGISTER

Auto Next Page Disable

Setting this bit disables automatic next page exchange in 1000BASE-T.

Advertising of next pages then depends on the value of the Next Page bit of

the Auto Negotiation Advertisement Register. In this case, if Next Page is

cleared, only the base page is sent.

0 = Normal operation

1 = Automatic next page is disabled

R/W

3:2

RESERVED

ENERGYON

This bit indicates whether energy is detected on the line. It is reset to “1” by

a hardware reset. When a software reset is asserted, this bit is cleared. If

this bit was set prior to a software reset, it will cause the INT7 bit of the

Interrupt Source Flags Register to be set. Therefore, after a software or

hardware reset, the INT7 bit should be cleared by writing a “1” to it.

Refer to Section 3.5, "Interrupt Management," on page 21 for additional

ENERGYON information.

Semi Crossover Enable

Setting this register enables semi cross over.

0 = Disable Semi cross over

1 = Enable Semi cross over

Note:

Refer to Section 3.2, "HP Auto-MDIX," on page 16 for additional

information.

R/W

Index (In Decimal): 18

Size:

16 bits

Bits

Description

Type

Default

Enable RXDV Early Assertion

Setting this bit enables early assertion of RXDV in 10BASE-T. RXDV is

asserted before the SFD.

0 = Disable

1 = Enable

R/W

10BT HD Loopback Disable

Setting this bit disables MII loopback in 10BASE-T half duplex mode.

0 = normal operation

1 = activates PHYT_10 test mode

R/W

NASR

000000b

13:8

RESERVED

CRC Error Counter Data Source

Setting this bit changes the data source of the 1000BASE-T CRC error

counter.

0 = Data source in 1000BASE-T received data

1 = Data source in 1000BASE-T transmitted data

R/W

MCLK25EN

Enable an 25Mhz MAC clock output.

0 = 125MHz

1 = 25MHz

RESERVED

Bits

Description

Type

Default

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