ADS5400IPZP datasheet(13/55 Pages) TI1

13 / 55 page

CLKINP

RESETP

CLKOUT isresetafter 3.5 CLKINcycles (+ tPD-CLKDIV2 )

Phase 0: CLKOUT indesired

stateafterpowerup

Phase 1: misalignedby

1 clockafterpowerup

tPD-CLKDIV2

tRSU

tRH

DATA BUS A

SYNCOUTA

(OVRA pins)

Sync

SampleNandRESET pulse

capturedhere

CLKOUTAP

IfSYNCmodeisenabled,

theOVRA pinsbecomeSYNCOUTA pins

LatencyofNandSYNCOUTA arematchedto 7 CLKINcycles

tsu

PD-ADATA

N+1

N-1

tCLKL

tCLKH

N+1

DIFFERENTIAL

ANALOGINPUT

(INP-INN)

Aperture

delay

N+2

output

N+1

output

ADS5400

www.ti.com

SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016

Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase

will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT

phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of

repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, to keep the CLKOUT

phase the same with each RESET event. SYNCOUTA transitions with the same latency as the sample that is present

when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse,

which behaves as a data bit. Bus B is not active in single bus mode.

Figure 1. Single Bus Mode

Submit Documentation Feedback

Product Folder Links: ADS5400

ADS5400IPZP bảng dữ liệu(PDF) 13 Page - Texas Instruments

ADS5400IPZP bảng dữ liệu(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

bảng dữ liệu tải về

Link URL