ADS5400IPZP datasheet(16/55 Pages) TI1

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CLKINP

RESETP

tRSU

tRH

DATA BUSB

SYNCOUTB

(OVRBpins)

IfSYNCmodeisenabled,

theOVRBpinsbecomeSYNCOUTBpins

Sync

CLKOUTAP

CLKOUTBP

tPD-CLKDIV4

tPD-BDATA

Phase 0: CLKOUT indesired

stateafterpowerup

Phase 1: misalignedby 1

clockafterpowerup

Phase 2: misalignedby 2

clocksafterpowerup

Phase 3: misalignedby 3

clocksafterpowerup

N+1

DATA BUS A

LatencyofN+1is7.5CLKINcycles

tPD-ADATA

CLKOUT isresetafter 7.5 CLKINcycles (+ tPD-CLKDIV4 )

ThephaseofdatashownpriortoresetmatchesCLKOUT inphase 0

SampleNandRESET

pulsecapturedhere

N+1

N, N+1

output

LatencyofNandSYNCOUTBarematchedto8.5 CLKINcycles

tsu

ADS5400

SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016

www.ti.com

Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase

will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT

phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of

repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, to keep the CLKOUT

phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present

when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse,

which behaves as a data bit.

Figure 4. Dual Bus Mode - Aligned, CLKOUT Divide By 4

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