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CAP1188 bảng dữ liệu(PDF) 49 Page - Microchip Technology |
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CAP1188 bảng dữ liệu(HTML) 49 Page - Microchip Technology |
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49 / 79 page ![]() 2015 Microchip Technology Inc. DS00001620C-page 49 CAP1188 Bit 3-2 - STBY SAMP_TIME[1:0] - Determines the time to take a single sample when the device is in Standby as shown in Table 6-38. Bits 1 - 0 - STBY_CY_TIME[2:0] - Determines the overall cycle time for all measured channels during standby operation as shown in Table 6-39. All measured channels are sampled at the beginning of the cycle time. If additional time is remaining, the device is placed into a lower power state for the remaining duration of the cycle. APPLICATION NOTE: The programmed cycle time is only maintained if the total averaging time for all samples is less than the programmed cycle. The STBY_AVG[2:0] bits will take priority so that if more samples are required than would normally be allowed during the cycle time, the cycle time will be extended as necessary to accommodate the number of samples to be measured. 6.22 Standby Sensitivity Register The Standby Sensitivity register controls the sensitivity for sensor inputs that are active in Standby. Bits 2 - 0 - STBY_SENSE[2:0] - Controls the sensitivity for sensor inputs that are active in Standby. The sensitivity set- tings act to scale the relative delta count value higher or lower based on the system parameters. A setting of 000b is the most sensitive while a setting of 111b is the least sensitive. At the more sensitive settings, touches are detected for a smaller delta C corresponding to a “lighter” touch. These settings are more sensitive to noise however and a noisy envi- ronment may flag more false touches than higher sensitivity levels. APPLICATION NOTE: A value of 128x is the most sensitive setting available. At the most sensitivity settings, the MSB of the Delta Count register represents 64 out of ~25,000 which corresponds to a touch 10 1 32 11 0 64 1 1 1 128 TABLE 6-38: STBY_SAMP_TIME BIT DECODE STBY_SAMP_TIME[1:0] Sampling Time 10 0 0 320us 0 1 640us 1 0 1.28ms (default) 1 1 2.56ms TABLE 6-39: STBY_CY_TIME BIT DECODE STBY_CY_TIME[1:0] Overall Cycle Time 10 0 0 35ms 0 1 70ms (default) 1 0 105ms 1 1 140ms TABLE 6-40: STANDBY SENSITIVITY REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 42h R/W Standby Sensitiv- ity - - - - - STBY_SENSE[2:0] 02h TABLE 6-37: STBY_AVG BIT DECODE (CONTINUED) STBY_AVG[2:0] Number of Samples Taken per Measurement 21 0 |
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