DLPC900ZPC datasheet(35/72 Pages) TI1

35 / 72 page

Port 1

Port 2

Peripherals

GPIO

I2C

USB

PWM

UART

Memory

Controller

DRAM

SSP

DMD

Controller

Pixel

Data

Processing

CPU BUS

MEMORY DMA BUS

Formatter

LED

Triggers

Pattern

Sequencer

ARM

PLL

Reset

JTAG

ICE

Clock

RAM

Flash

Interface

Digital Input

PLLD

PLLM

PLLS

Crystal

POSENSE

PWRGOOD

JTAG

LED

Triggers

DMD Control and

Data Interface

Debug

PWM

USB

I2C

GPIO

Digital Input

GND

VDD33

VDDC

VDD18

DMD

Serial Interface

DLPC900

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DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

7 Detailed Description

7.1 Overview

The DLPC900 controller processes the digital input image and converts the data into the digital format needed by

the DLP9000 or the DLP6500. The DLP9000 and the DLP6500 reflect light by using binary pulse-width-

modulation (PWM) for each micromirror. For further details, refer to the DLP9000 or the DLP6500 data sheets.

The DLPC900 combined with a DLP6500 supports a wide variety of resolutions from SVGA to 1080p. When

accurate pattern display is needed, a native 1080p resolution source is used for a one-to-one association with

the corresponding micromirror on the DLP6500.

The DLPC900 combined with a DLP9000 supports only native WQXGA resolution for a one-to-one association

with the corresponding micromirror on the DLP9000. Both combinations are well-suited for structured light,

additive manufacturing, or digital exposure applications.

7.2 Functional Block Diagram

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