DLPC900ZPC datasheet(2/72 Pages) TI1

2 / 72 page

DLPC900

DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

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Table of Contents

Features .................................................................. 1

Detailed Description ............................................ 35

7.1

Overview ................................................................. 35

Applications ........................................................... 1

7.2

Functional Block Diagram ....................................... 35

Description ............................................................. 1

7.3

Feature Description................................................. 36

Revision History..................................................... 3

7.4

Device Functional Modes........................................ 38

Pin Configuration and Functions ......................... 4

Application and Implementation ........................ 41

Specifications....................................................... 20

8.1

Application Information............................................ 41

6.1

Absolute Maximum Ratings ................................... 20

8.2

Typical Applications ................................................ 41

6.2

ESD Ratings............................................................ 20

Power Supply Recommendations ...................... 48

6.3

Recommended Operating Conditions ..................... 21

9.1

System Power Regulation ...................................... 48

6.4

Thermal Information ................................................ 21

9.2

System Environment and Defaults.......................... 49

6.5

Electrical Characteristics......................................... 22

9.3

System Power-Up Sequence .................................. 49

6.6

System Oscillators Timing Requirements .............. 25

9.4

System Reset Operation ......................................... 51

6.7

Reset Timing Requirements ................................... 26

Layout................................................................... 52

6.8

JTAG Interface: I/O Boundary Scan Application

Timing Requirements ............................................... 27

10.1

Layout Guidelines ................................................. 52

6.9

JTAG Interface: I/O Boundary Scan Application

10.2

Layout Example .................................................... 63

Switching Characteristics ......................................... 27

10.3

Thermal Considerations ........................................ 65

6.10

Programmable Output Clocks Switching

Device and Documentation Support ................. 66

Characteristics ......................................................... 28

11.1

Device Support...................................................... 66

6.11

Port 1 and 2 Input Pixel Interface Timing

11.2

Documentation Support ........................................ 67

Requirements........................................................... 29

11.3

Community Resources.......................................... 67

6.12

Two Pixels Per Clock (48-bit Bus) Timing

11.4

Trademarks ........................................................... 67

Requirements........................................................... 30

11.5

Electrostatic Discharge Caution ............................ 67

6.13

SSP Switching Characteristics.............................. 30

11.6

Glossary ................................................................ 68

6.14

DMD Interface Switching Characteristics ............. 32

Mechanical, Packaging, and Orderable

6.15

DMD LVDS Interface Switching Characteristics ... 33

Information ........................................................... 68

6.16

Source Input Blanking Requirements ................... 34

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