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CDCE62005 bảng dữ liệu(PDF) 72 Page - Texas Instruments |
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CDCE62005 bảng dữ liệu(HTML) 72 Page - Texas Instruments |
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72 / 85 page  CDCE62005 SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 www.ti.com Typical Application (continued) Step 4: The PLL loop bandwidth of the CDCE62005 is recommended to be set according to the phase noise profile of its reference input and the phase noise profile of the onboard VCO clock. It is recommended to set the PLL loop bandwidth as the crossover point of the reference input phase noise and the phase noise of the VCO clock. When the input clock is clean and any near-frequency offsets are better than the VCO clock, it is beneficial for the PLL bandwidth to be set at several hundred kHz as determined by the crossover point. Figure 48 shows a typical 400-kHz Loop filter. Figure 48. On-Chip Loop Filter Circuit for 400-kHz Loop Bandwidth (Loop Settings in Figure 47, CP Current at 3.5mA) 72 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: CDCE62005 |
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