CDCE62005 datasheet(39/85 Pages) TI1

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OutputDivider 2

OutputDivider 3

AUX

OUT

CDCE62005

www.ti.com

SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015

Table 20. Output Synchronization Procedure

R4.1

R6.20

COMMENTS

The synchronized outputs will be enabled after ~6 µs delay and the next rising edge of the

reference clock and selected clock of output multiplexer.

The synchronized outputs will be enabled after ~6 µs delay and the next rising edge of

Toggling SYNC Pin or

selected clock of output multiplexer (reference Figure 26 (a)).

Bit (R8.8) from low to

The synchronized outputs will be enabled with the next rising edge of reference clock & the

high

selected clock of output multiplexer (reference Figure 26 (c)).

The synchronized outputs will be enabled with the next rising edge of the selected clock of

output multiplexer (reference Figure 26 (b)).

Toggling SYNC Pin or

All outputs are disabled.

Bit (R8.8) from high to

low

8.3.5.15 Auxiliary Output

Figure 27 shows the auxiliary output port. Table 21 lists how the auxiliary output port is controlled. The output

buffer supports a maximum output frequency of 250 MHz and drives at LVCMOS levels. Refer to Table 13 for the

list of divider settings that establishes the output frequency.

Figure 27. CDCE62005 Auxiliary Output

Table 21. CDCE62005 Auxiliary Output Settings

BIT NAME

→

AUXFEEDSEL

AUXOUTEN

AUX OUTPUT SOURCE

→

6.25

6.24

OFF

Divider 2(1)

Divider 3(1)

(1)

If Divider 2 or Divider 3 is set to divide by 1 and AUXOUT is selected from divide by 1, then AUXOUT

will be disabled even if the AUXOUTEN bit (6.24) is high.

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