TAS5548DCAR datasheet(53/116 Pages) TI1

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TAS5548

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SLES270A – NOVEMBER 2012 – REVISED APRIL 2015

7.6 Register Maps

7.6.1 Serial-Control I2C Register Summary

The TAS5548 slave write address is 0x36 and the read address is 0x37. See Serial-Control Interface Register

Definitions for complete bit definitions.

Note: Default stat is read immediately after device reset.

TOTAL

I2C

DESCRIPTION OF CONTENTS

DEFAULT STATE (hex)

BYTES

SUBADDRESS

0x01

General status register

ID code for the TAS5548

0x02

Error status register

CLIP and frame slip errors

PWM high pass, clock set, unmute

0x03

System control register 1

select, PSVC select

Automute, Shutdown, Line out,

0x04

System control register 2

SDOUT

Channel configuration

Configure channels 1, 2, 3, 4, 5, 6, 7,

0x05–0x0C

1/reg.

control registers

and 8

Headphone configuration

0x0D

Configure headphone output

control register

0x0E

Serial data interface control

Set serial data interface to right-

justified, I2S, or left-justified.

0x0F

Soft mute register

Soft mute for channels 1, 2, 3, 4, 5, 6,

7, and 8

0x10

Energy Managers Register

See Table 23

0x11

Reserved

Do not Read or Write

RESERVED

0x12

Oscillator Trim

See

0x13

Reserved

Do not Read or Write

RESERVED

0x14

Automute control register

Set automute delay and threshold

0x15

Automute PWM threshold

Set PWM automute threshold; set

and back-end reset period

back-end reset period

0x16

Modulation Limit Reg

Set modulation index ch1 and ch2

(ch1 and 2)

0x17

Modulation Limit Reg

Set Modulation Index ch3 and ch4

(ch3 and 4)

0x18

Modulation Limit Reg

Set Modulation Index ch5 and ch6

(ch5 and 6)

0x19

Modulation Limit Reg

Set Modulation Index ch7 and ch8

(ch7 and 8)

0x1A

Reserved

Do not Read or Write

RESERVED

0x1B

IC Delay Channel 0

See Table 28

0x1C

IC Delay Channel 1

See Table 28

0x1D

IC Delay Channel 2

See Table 28

0x1E

IC Delay Channel 3

See Table 28

0x1F

IC Delay Channel 4

See Table 28

0x20

IC Delay Channel 5

See Table 28

0x21

IC Delay Channel 6

See Table 28

0x22

IC Delay Channel 7

See Table 28

0x23

IC Offset Delay Reg

See Table 28

0x24

PWM sequence timing

See

0x25

PWM and Energy Manager

See Table 30

Control Register

0x26

Reserved

Do not Read or Write

RESERVED

0x27

Individual Channel

See Table 31

Shutdown

0x28–0x2F

Reserved

Do not Read or Write

RESERVED

0x30

Input_Mux_ch1 and 2

See Table 32 and Table 33

0x31

Input_Mux_ch3 and 4

See Table 32 and Table 33

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