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tên linh kiện TAS5548DCAR
Giải thích chi tiết về linh kiện  8-Channel HD Compatible Audio Processor
PDF  116 Pages
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TAS5548DCAR bảng dữ liệu(HTML) 4 Page - Texas Instruments

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TAS5548
SLES270A – NOVEMBER 2012 – REVISED APRIL 2015
www.ti.com
Pin Functions (continued)
PIN
5-V
TYPE
TERMINATION
DESCRIPTION
TOLERANT
NAME
NO.
HP_SEL
17
DI
5 V
Pullup
Headphone/speaker selector. When a logic low is applied, the headphone is
selected (speakers are off). When a logic high is applied, speakers are selected
(headphone is off).
LRCLK
22
DI
5 V
Pulldown
Serial-audio data left/right clock (sampling-rate clock)
LRCLKO /
31
DIO
5V
Pulldown
LRCLK for I2S OUT. Can also be used as LRCKIN_2 (I2S Input for SDIN2_x
LRCKIN_2
and SRC Bank 2)
XTALI
11
DI
1.8 V
XTAL input. Connect to external 12.288 MHz XTAL
MUTE
19
DI
5 V
Pullup
Soft mute of outputs, active-low (muted signal = a logic low, normal operation =
a logic high). The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
XTALO
12
DO
XTAL input. Connect to external 12.288 MHz XTAL
PDN
18
DI
5 V
Pullup
Power down, active-low. PDN powers down all logic and stops all clocks
whenever a logic low is applied. The I2C parameters are preserved through a
power-down cycle, as long as RESET is not active.
PLL_FLTM
6
AIO
PLL negative filter.
PLL_FLTP
7
AIO
PLL positive filter.
PSVC/MCLKO
33
DO
Power-supply volume control PWM output or MCKO for external ADC (SDIN5
Source)
PWM_HPM_L
1
DO
PWM left-channel headphone (differential –)
PWM_HPM_R
3
DO
PWM right-channel headphone (differential –)
PWM_HPP_L
2
DO
PWM left-channel headphone (differential +)
PWM_HPP_R
4
DO
PWM right-channel headphone (differential +)
PWM_M_1
38
DO
PWM 1 output (differential –)
PWM_M_2
40
DO
PWM 2 output (differential –)
PWM_M_3
42
DO
PWM 3 output (differential –)
PWM_M_4
44
DO
PWM 4 output (differential –)
PWM_M_5
53
DO
PWM 5 output (lineout L) (differential –)
PWM_M_6
55
DO
PWM 6 output (lineout R) (differential –)
PWM_M_7
46
DO
PWM 7 output (differential –)
PWM_M_8
48
DO
PWM 8 output (differential –)
PWM_P_1
39
DO
PWM 1 output (differential +)
PWM_P_2
41
DO
PWM 2 output (differential +)
PWM_P_3
43
DO
PWM 3 output (differential +)
PWM_P_4
45
DO
PWM 4 output (differential +)
PWM_P_5
54
DO
PWM 5 output (lineout L) (differential +)
PWM_P_6
56
DO
PWM 6 output (lineout R) (differential +)
PWM_P_7
47
DO
PWM 7 output (differential +)
PWM_P_8
49
DO
PWM 8 output (differential +)
RESET
16
DI
5 V
Pullup
System reset input, active-low. A system reset is generated by applying a logic
low to this terminal. RESET is an asynchronous control signal that restores the
TAS5548 to its default conditions, sets the valid output low, and places the
PWM in the hard-mute state (Non PWM Switching). Master volume is
immediately set to full attenuation. On the release of RESET, if PDN is high, the
system performs a 4- to 5-ms device initialization and sets the volume at mute.
SCL
21
DI
5 V
I2C serial-control clock input/output
SCLK
23
DI
5 V
Pulldown
Serial-audio data clock (shift clock) input
SCLKO /
30
DIO
5V
Pulldown
Serial data clock out. I2S bit clock out. Can also be used as SCLKIN_2 (I2S
SCLKIN_2
Input for SDIN2_x and SRC Bank 2)
SDA
20
DIO
5 V
I2C serial-control data-interface input/output
SDIN1
24
DI
5 V
Pulldown
Serial-audio data bank 1 input 1 is one of the serial-data input ports and goes
into the 1st SRC Bank. Four discrete (stereo) data formats and is capable of
inputting data at 64 fS.
SDIN2
25
DI
5 V
Pulldown
Serial-audio data bank 1 input 2 is one of the serial-data input ports and goes
into the 1st SRC Bank. Four discrete (stereo) data formats and is capable of
inputting data at 64 fS.
4
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Product Folder Links: TAS5548



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