TAS5548DCAR datasheet(39/116 Pages) TI1

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Biquads

Series

Bass

and

Treble

DRC

Bass and Treble

Bypass

Bass

and

Treble

Inline

Pre-

Volume

Post-

Volume

DRC

Bypass

DRC

Inline

B0016-02

From Input Mixer

To Output Mixer

Loudness

Channel Volume

Master

Volume

Max

Volume

TAS5548

www.ti.com

SLES270A – NOVEMBER 2012 – REVISED APRIL 2015

Table 11. DRC Recommended Changes From TAS5548 Defaults

I2C

RECOMMENDED

DEFAULT TIME

TIME

DEFAULT HEX

SUBADDRESS

HEX VALUE

CONSTANT (ms)

0x98

DRC1 energy

0000 883F

DRC1 (1 – energy)

007F 77C0

0x9C

DRC1 attack

0000 883F

DRC1 (1 – attack)

007F 77C0

DRC1 decay

0001 538F

0000 0056

DRC1 (1 – decay)

007E AC70

003F FFA8

0x9D

DRC2 energy

0000 883F

DRC2 (1 – energy)

007F 77C0

0xA1

DRC2 attack

0000 883F

DRC2 (1 – attack)

007F 77C0

DRC2 decay

0001 538F

0000 0056

DRC2 (1 – decay)

007E AC70

003F FFA8

Recommended DRC setup flow if the defaults are used:

•

After power up, load the recommended hex value for DRC1 and DRC2 decay and (1 – decay). See Table 11.

•

Enable either the pre-volume or post-volume DRC using I2C registers 0x96 and 0x97. Note that to avoid a

potential timing problem, there is a 10-ms delay between a write to 0x96 and a write to 0x97.

Recommended DRC setup flow if the DRC design uses values different from the defaults:

•

After power up, load all DRC coefficients per the DRC design.

•

Enable either the pre-volume or post-volume DRC. Note that to avoid a potential timing problem, there is a

10-ms delay between a write to 0x96 and a write to 0x97.

Figure 36 shows the positioning of the DRC block in the TAS5548 processing flow. As seen, the DRC input can

come either before or after soft volume control and loudness processing.

Figure 36. DRC Positioning in TAS5548 Processing Flow

Figure 37 illustrates a typical DRC transfer function.

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