PS081 datasheet(57/155 Pages) AMSCO

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3-34

PSØ81

Zero Drift of Full Bridge Standard Wiring

In the packaged version of PS081 there is some systematic offset drift due to different bond wire

lengths. This zero drift is ±10 nV/V/K and the same for every chip. Because of the nature of this

drift it can be easily compensated on the PCB by cross-matching the different bond wire length on

the PCB.

To compensate this systematical drift the trace from SG-B1 to the connection pad of the load cell

wire should be (t.b.d.) mm longer than the trace from SG-A2 to the connection pad. SG-A1 and SG-

B2 should have the same length.

Please note: In any case, the main source of the drift is not the electronic. PICOSTRAIN and also

a good AD-converter have 5 to 10 times better drift values than a good load cell. Therefore, if the

system performance should be significantly increased, the drift of the load cell has to be reduced.

PS081 can solve this task by software with the Mult_TKO possibility.

3.6.7

Mult_UB - Power Supply Rejection

PS081 measures frequently the supply voltage. The measured voltage can be used to correct the

dependency of the gain from the voltage. It is switched on by configuration bit mult_en_ub = 1.

Factor mult_ub[7:0] defines the control ratio of the voltage measurement. The control ratio is gene-

rally very low. The result of the strain measurement will be corrected according to

HB = HB/(1 + UB*[-128 ... 127] / 221).

The standard setting for Mult_UB is 0xF7.

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