AX8052F151 datasheet(3/51 Pages) ONSEMI

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Table of Contents

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AX8052F151

Reset and Interrupts ..................................................................................................29

Debugging ................................................................................................................29

5.2. Timer, Output Compare and Input Capture ...................................................................30

5.3. UART .......................................................................................................................30

5.4. SPI Master/Slave Controller ........................................................................................30

5.5. ADC, Analog Comparators and Temperature Sensor.......................................................31

5.6. DMA Controller ..........................................................................................................32

5.7. AES Engine ...............................................................................................................32

5.8. Crystal Oscillator (RF reference oscillator).....................................................................32

5.9. SYSCLK Output..........................................................................................................33

5.10.

Power-on-reset (POR) and RESET_N Input ...............................................................33

5.11.

Ports ...................................................................................................................34

6. Transceiver ............................................................................................................ 35

6.1. RF Frequency Generation Subsystem ...........................................................................35

VCO .........................................................................................................................35

VCO Auto-Ranging .....................................................................................................35

Loop Filter and Charge Pump.......................................................................................36

Registers...................................................................................................................36

6.2. RF Input and Output Stage (ANTP/ANTN) .....................................................................37

LNA ..........................................................................................................................37

I/Q Mixer ..................................................................................................................37

PA............................................................................................................................37

6.3. Analog IF Filter..........................................................................................................37

6.4. Digital IF Channel Filter and Demodulator.....................................................................37

Registers...................................................................................................................38

6.5. Encoder....................................................................................................................38

6.6. Framing and FIFO ......................................................................................................39

HDLC Mode ...............................................................................................................40

RAW Mode ................................................................................................................40

RAW Mode with Preamble Match ..................................................................................40

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