AX8052F151 datasheet(9/51 Pages) ONSEMI

9 / 51 page

Pin Function Descriptions

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AX8052F151

Symbol

Pin(s)

Type

Description

VREG

Regulated output voltage

VDDA pins must be connected to this supply voltage

A 1µF low ESR capacitor to GND must be connected to

this pin

CLK16P

Crystal oscillator input/output (RF reference)

CLK16N

Crystal oscillator input/output (RF reference)

GND

Center pad

Ground on center pad of QFN, must be connected

A = analog signal

I/O = digital input/output signal

I = digital input signal

= not to be connected

O = digital output signal

= power or ground

PU = pull-up

PD = pull-down

All digital inputs are Schmitt trigger inputs, digital input and output levels are LVCMOS/LVTTL

compatible. Port A Pins (PA0 - PA7) must not be driven above VDD_IO, all other digital inputs are

5V tolerant. Pull-ups are programmable for all GPIO pins.

3.1. Alternate Pin Functions

GPIO Pins are shared with dedicated Input/Output signals of on-chip peripherals. The following

table lists the available functions on each GPIO pin.

GPIO

Alternate Functions

PA0

T0OUT

IC1

ADC0

PA1

T0CLK

OC1

ADC1

PA2

OC0

U1RX

ADC2

COMPI00

PA3

T1OUT

ADC3

LPXTALP

PA4

T1CLK

COMPO0

ADC4

LPXTALN

PA5

IC0

U1TX

ADC5

COMPI10

PA6

T2OUT

ADCTRIG

ADC6

COMPI01

PA7

T2CLK

COMPO1

ADC7

COMPI11

PB0

U1TX

IC1

EXTIRQ0

PB1

U1RX

OC1

PB2

IC0

T2OUT

PB3

OC0

T2CLK

EXTIRQ1

DSWAKE

PB4

U0TX

T1CLK

PB5

U0RX

T1OUT

PB6

DBG_DATA

PB7

DBG_CLK

PC0

SSEL

T0OUT

EXTIRQ0

PC1

SSCK

T0CLK

COMPO1

PC2

SMOSI

U0TX

PC3

SMISO

U0RX

COMPO0

PC4

COMPO1

ADCTRIG

EXTIRQ1

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