SM5901AF datasheet(21/31 Pages) NPC

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SM5901AF

13.3ms

VWA latch set

WAQV set

VWA(x)

VWA(x + 1)

YBLKCK

Microcontroller data set

Refer to Microcontroller interface

VWA

Values shown are for rate fs. The values are 1/2 those shown at rate 2fs.

Fig 2. YBLKCK and VWA relationship

The VWA is determined according to the YBLKCK

pin and WAQV command. Refer to the timing chart

below.

1.YBLKCK is a 75 Hz clock(HIGH) when used for

normal read mode and it is a 150Hz clock when

used for double-speed read mode. Both modes

clock are synchronized to the CD format block end

timing.

When this clock goes LOW, WA which is the write

address of internal encode sequence, is stored

(see note 2).

2.The microcontroller checks the subcode and, if

confirmed to be correct, generates a WAQV com-

mand (80H).

3.When the WAQV command is received, VWA is

updated according to the previously latched WA.

(note 2) Actually, there is a small time difference, or

gap, between the input data and YBLKCK. This gap

serves to preserves the preceding WA to protect

against incorrect operation.

RAM addresses

SM5901 has an 1M DRAM as the internal buffer.

and an external 1M DRAM can be also connected

to expand the memory to 2M bits.

Three kinds of addresses are used for external

RAM control.

WA (write address)

RA (read address)

VWA (valid write address)

Among these, VWA is the write address for con-

forming data whose validity has been confirmed.

Determination of the correctness of data read from

the CD is delayed relative to the encode write pro-

cessing, so VWA is always delayed relative to WA.

The region available for valid data is the area

between VWA-RA.

- Connect data work area

This is an area of memory reserved for connect

data. This area is 2Kbits.

Fig1. RAM addresses

VWA

Valid data

area

Connect data work area

VWA (valid write address)

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