GP2021 datasheet(34/62 Pages) MITEL

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GP2021

28.571429ns) for Complex_Input mode. The value stored in

the preset register can be modified in one of two ways: Either

toggling

the

INTERRUPT_PERIOD

FRONT_END_MODE bits of the SYSTEM_SETUP register,

or by writing to the PROG_ACCUM_INT location. Either of

these actions will overwrite the previous contents of the preset

value and either one or both methods may be used. If the

Interrupt Counter detects an edge on either the

INTERRUPT_PERIOD or FRONT_END_MODE bits it will

load one of four values in to the preset register, depending

upon the new value of both INTERRUPT_PERIOD and

FRONT_END_MODE. These four presets are as shown in

Table 12.

The value for INTERRUPT_PERIOD = Low and

FRONT_END_MODE = Low is also that loaded on a Master

Reset. Alternatively the ACCUM_INT counter may be loaded

by writing direct to the PROG_ACCUM_INT location. In this

case the new ACCUM_INT period is as follows:

ACCUM_INT Period = (PROG_ACCUM_INT + 1) * 7 (40MHZ)

(Real Input mode)

ACCUM_INT Period = (PROG_ACCUM_INT + 1) * 6 (35MHz)

(Complex Input mode)

PROG_TIC_HIGH,

PROG_TIC_LOW

(Write Address)

PROG_TIC_HIGH Bits 4 to 0: More significant 5 bits of

the TIC counter division ratio when programmed before a

PROG_TIC_LOW.

PROG_TIC_LOW Bits 15 to 0: Least significant 16 bits of the

TIC counter division ratio.

The PROG_TIC_HIGH and PROG_TIC_LOW register

locations

operate

conjunction

with

the

FRONT_END_MODE bit of the SYSTEM_SETUP register to

set the period of TIC. TIC is generated by a 21 bit binary down

counter when it reaches zero. It then loads to a preset value

stored in its preset register and starts to count down again. If

the preset value is P, the count sequence is P, P–1, P–2, ...,

1, 0, P, P–1. Hence, the counter divides by P+1 producing an

output with a period of (P+1) * clock period. Since the TIC

counter is clocked by the multi–phase clock, the clock period

is either 7 * clock period (nominally 40MHz i.e. 25ns) for

Real_Input mode or 6 * clock period (nominally 35MHz i.e.

28.571429ns) for Complex_Input mode. The value stored in

the preset register can be modified in one of two ways: Either

toggling

the

FRONT_END_MODE

bit

the

SYSTEM_SETUP register, switching into Complex_Input

mode, or by writing to the PROG_TIC_HIGH/_LOW locations.

Either of these actions will overwrite the previous contents of

the preset value. If the TIC Counter detects an edge on the

FRONT_END_MODE bit it will load one of two values into the

preset register, depending upon its new value. These two

presets are as shown in Table 13.

The value for FRONT_END_MODE = Low is also that

loaded on a Master Reset. Alternatively, the TIC counter may

be loaded by writing directly to the PROG_TIC locations. This

may be achieved in one of two ways: Either the

PROG_TIC_HIGH value can be written, followed by the

PROG_TIC_LOW value, (at which point the full 21 bits are

transferred

the

preset

just

the

PROG_TIC_LOW value may be written to modify the lower 16

bits of the preset value. It should be noted that in the former

case, the top 5 bits programmed as PROG_TIC_HIGH are

stored locally to the TIC counter and even if a write to

PROG_TIC_LOW does not directly follow the write to

PROG_TIC_HIGH, the next PROG_TIC_LOW write will still

transfer all 21 bits. It is also necessary to ensure that the write

PROG_TIC_HIGH

precedes

the

write

PROG_TIC_LOW, rather than follows it. One further point to

note is that the transfer of data to the TIC counter data latches

occurs under control of the multi–phase clock write cycle and

the write to the preset register happens subsequent to the

main internal write. To ensure correct operation, a write to

SYSTEM_SETUP, toggling the FRONT_END_MODE bit

should not be directly preceded or followed by a write to

PROG_TIC_LOW. In addition to the 300ns delay normally

required between write cycles, a further 100ns delay is

required between these two types of writes. A write to

SYSTEM_SETUP toggling the FRONT_END_MODE bit

followed directly by a PROG_TIC_HIGH / PROG_TIC_LOW

sequence is permissible, since the write to PROG_TIC_HIGH

does not instigate a change of the preset register contents

within the TIC counter.

Using the PROG_TIC write locations the TIC period is as

follows:

TIC Period

= ((PROG_TIC_HIGH * 65536) +

(Real_Input)

PROG_TIC_LOW+1)*7/(40MHZ)

TIC Period

= ((PROG_TIC_HIGH * 65536) +

(Complex_Input)

PROG_TIC_LOW+1) * 6/(35MHZ)

Table 12: ACCUM_INT Period settings

FRONT_END_MODE

INTERRUPT_PERIOD

Preset

ACCUM_INT Period

(In SYSTEM_SETUP)

(in SYSTEM_SETUP)

Low (Real_Input mode)

Low

0x0B45

(2885+1)* (7/40MHz) = 505.0500

µs

Low (Real_Input mode)

High

0x1313

(4883+1)* (7/40MHz) = 854.70000

µs

High (Complex_Input mode)

Low

0x0B81

(2945+1)* (6/35MHz) = 505.02857

µs

High (Complex_Input mode)

High

0x1379

(4985+1)* (6/35MHz) = 854.74286

µs

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