GP2021 datasheet(17/62 Pages) MITEL

17 / 62 page

GP2021

ARM System Mode

ARM System Mode, as shown in Fig 14, allows the

GP2021 to be interfaced with an ARM60 microprocessor and

external memory devices (i.e RAM, ROM, EEPROM,

EPROM, Flash) without the need for external glue logic.

Address Map

Both the GP2021 and external memory devices are

memory mapped into 1 Mbyte segments by A<22:20> as

shown in Table 7.

Decoded

A22

A21

A20

Device selected

output

ROM

NROM

RAM

NRAM

Correlator

Support functions

EEPROM

NEEPROM

User defined

NSPARE_CS

Not Decoded

Table 7 ARM system map

Control Signals

The GP2021 uses the ARM60 control signals NBW,

NMREQ and NRW to generate the processor clock MCLK and

the control signals ARM_ALE and DBE to match the timing

requirements of the various memory devices .

The memory interface is via the memory chip select lines

( NRAM, NEEPROM, NROM and NSPARE_CS) , the Read

line (NRD) and the byte write select outputs ( NW<3:0> ).

ARM System Timing

The GP2021 timing diagrams for each of the memory

interfaces ( EEPROM, RAM, ROM, SPARE), and ARM60

areshown in the section Electrical Characteristics.

Wait State Generation

To allow access to slow peripherals or memory, the clock

(MCLK) to the ARM60 microprocessor may be stretched in

either Phase 1 (Low) or Phase 2 (High), thus allowing wait

states to be introduced (where a wait state is defined as being

one MCLK period long).

The GP2021 introduces one wait state for accesses to the

Real Time Clock, Dual UART and System Control registers,

as shown in Fig 15. Correlator accesses, as shown in Fig 19

incur one wait state; subsequent accesses being prevented

from contravening the Correlator requirements (see

Correlator Functional Description) by adding several wait

states.

In order to ensure compatibility with variety of memory

devices, the ROM interface is programmable with between

one to three wait states, while the EEPROM and SPARE

interfaces can be programmed with between three to six wait

states via the Wait State Register. For further information on

the Wait State Register, refer to Detailed Description of

Registers. Read and write cycles for the RAM, EEPROM (or

Spare) and ROM interfaces are shown in Figs 16–18.

During a read cycle from Flash Memory, the output disable

to data bus release time, could be greater than 25 ns. Hence

in order to avoid bus contention, the nominal period of MCLK

is stretched by 25 ns during the following cycle.

The ARM60 is able to perform either byte or word ( 4 bytes

wide) writes to memory. All registers within the GP2021 are

word aligned, with only write accesses to external RAM being

either byte or word aligned. The signal NBW is used to indicate

either a byte or word write request, with A<1:0> performing

byte selection.

Decoding of NBW and A<1:0> is performed by the

Microprocessor Interface, with NW<3:0> being the byte write

select outputs to memory. During a word write all four of the

outputs NW<3:0> will be active.

Note that the register addresses for the Correlator and

Support Functions are as shown in the GP2021 Register Map.

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