GP2021 datasheet(16/62 Pages) MITEL

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GP2021

WREN

READ

NCS

A<9:2>

D<15:0>

Read

Write

Delayed Write

Delayed Read

NOTE: OP and IP are with respect to the GP2021. OP denotes a GP2021 Output, IP denotes a processor output.

300ns (314ns)

Fig.13 Correlator Bus Timing - Write to Write and Write to Read Timings

ARM60

GP2021

Memory

NRAM

NROM

NEEPROM

NSPARE_CS

NW<3:0>

NRD

D<15:0>

A<9:2>

A<19:10>

DBE

ARM_ALE

MCLK

NRW

NMREQ

NBW

D<15:0>

A<9:2>

A<22:20>, A<1:0>

NOPC

ABORT

A<19:10>

(NRESET_OP, ACCUM_INT and MEAS_INT not shown)

Fig.14 ARM System Mode

Note that the exact number of wait states which need to be

inserted after a correlator write is not fixed. If the processor

were to perform a correlator write then spend 400ns

accessing a different peripheral, subsequent correlator reads

and writes would incur no additional delay. It is anticipated

that correlator wait states will be generated by either one or

two external counters, preset on the falling edge of a correlator

write, and which then count down to zero. Only once the

counter has reached zero may the next correlator access

either complete (write) or start (read).

A series of correlator reads and writes are shown in Fig.13.

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