AX5243 datasheet(39/65 Pages) ONSEMI

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Circuit Description

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AX5243

5.16. Serial Peripheral Interface (SPI)

The AX5243 can be programmed via a four wire serial interface according SPI using the

pins CLK, MOSI, MISO and SEL. Registers for setting up the AX5243 are programmed

via the serial peripheral interface in all device modes.

When the interface signal SEL is pulled low, a configuration data stream is expected on

the input signal pin MOSI, which is interpreted as D0...Dx, A0...Ax, R_N/W. Data read

from the interface appears on MISO.

Figure 6 shows a write/read access to the interface. The data stream is built of an

address byte including read/write information and a data byte. Depending on the R_N/W

bit and address bits A[6..0], data D[7..0] can be written via MOSI or read at the pin

MISO. R_N/W = 0 means read mode, R_N/W = 1 means write mode.

Most registers are 8 bits wide and accessed using the waveforms as detailed in Figure 7.

The most important registers are at the beginning of the address space, i.e. at addresses

less than 0x70. These registers can be accessed more efficiently using the short address

form, which is detailed in Figure 6.

Some registers are longer than 8 bits. These registers can be accessed more quickly than

by reading and writing individual 8 bit parts. This is illustrated in Figure 8. Accesses are

not limited by 16 bits either, reading and writing data bytes can be continued as long as

desired. After each byte, the address counter is incremented by one. Also, this access

form works with long addresses.

During the address phase of the access, the AX5243 outputs the most important status

bits. This feature is designed to speed up the software decision on what to do in an

interrupt handler.

The status bits contain the following information:

SPI bit

cell

Status

Meaning / Register Bit

1 (when transitioning out of deep sleep mode, this bit transitions from 0  1 when

the power becomes ready)

S14

PLL LOCK

S13

FIFO OVER

S12

FIFO UNDER

S11

THRESHOLD FREE (

FIFOFREE > FIFOTHRESH)

S10

THRESHOLD COUNT (

FIFOCOUNT > FIFOTHRESH)

FIFO FULL

FIFO EMPTY

PWRGOOD (not BROWNOUT)

PWR INTERRUPT PENDING

RADIO EVENT PENDING

XTAL OSCILLATOR RUNNING

WAKEUP INTERRUPT PENDING

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