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AX5243 bảng dữ liệu(PDF) 22 Page - ON Semiconductor

tên linh kiện AX5243
Giải thích chi tiết về linh kiện  Advanced high performance ASK
PDF  65 Pages
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AX5243 bảng dữ liệu(HTML) 22 Page - ON Semiconductor

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Specifications
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AX5243
22
Overall State Transition Times
SYMBOL
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
Ttx_on
TX startup time
Powermodes:
STANDBY to FULLTX
Note 1, 2
40
40
+
1 x tbit
μs
Trx_on
RX startup time
Powermodes:
STANDBY to FULLRX
190
μs
Trx_rssi
RX startup time to valid RSSI
Powermodes:
STANDBY to FULLRX
Modulation (G)FSK
Note 1, 2
270
+
3 x tbit
μs
Trx_data
RX startup time to valid data
at full sensitivity/selectivity
190
+
9 x tbit
μs
Trxtx
RX to TX switching
Powermodes:
FULLRX to FULLTX
62
μs
Ttxrx
TX to RX switching
(to preamble start)
Powermodes:
FULLTX to FULLRX
200
Thop
Frequency hop
Switch between
frequency defined in
register FREQA and
FREQB
30
μs
Notes
1.
tbit depends on the datarate, e.g. for 10 kbps tbit = 100 μs
2.
In wire mode there is a processing delay of typically 6 x tbit between antenna and DCLK/DATA pins
SPI Timing
SYMBOL
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
Tss
SEL falling edge to CLK rising edge
10
ns
Tsh
CLK falling edge to SEL rising edge
10
ns
Tssd
SEL falling edge to MISO driving
0
10
ns
Tssz
SEL rising edge to MISO high-Z
0
10
ns
Ts
MOSI setup time
10
ns
Th
MOSI hold time
10
ns
Tco
CLK falling edge to MISO output
10
ns
Tck
CLK period
Note 1
50
ns
Tcl
CLK low duration
40
ns
Tch
CLK high duration
40
ns
Notes
1.
For SPI access during power-down mode the period should be relaxed to 100 ns.
For a figure showing the SPI timing parameters see section 5.16: Serial Peripheral
Interface (SPI).



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