PIC16C72-04SLASHSP datasheet(5/124 Pages) MICROCHIP

5 / 124 page

PIC16C72 Series

Preliminary

DS39016A-page 5

2.0

MEMORY ORGANIZATION

There are two memory blocks in PIC16C72 Series

devices. These are the program memory and the data

memory. Each block has its own bus, so that access to

both blocks can occur during the same oscillator cycle.

The data memory can further be broken down into the

general purpose RAM and the Special Function

Registers (SFRs). The operation of the SFRs that

control the “core” are described here. The SFRs used

to control the peripheral modules are described in the

section discussing each individual peripheral module.

Additional information on device memory may be found

in the PICmicro™ Mid-Range Reference Manual,

DS33023.

2.1

Program Memory Organization

PIC16C72 Series devices have a 13-bit program

counter capable of addressing a 2K x 14 program

memory space. The address range for this program

memory is 0000h - 07FFh. Accessing a location above

the physically implemented address will cause a wrap-

around.

The reset vector is at 0000h and the interrupt vector is

at 0004h.

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK

PC<12:0>

0000h

0004h

0005h

07FFh

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

0800h

PIC16C72-04/SP bảng dữ liệu(PDF) 5 Page - Microchip Technology

PIC16C72-04/SP bảng dữ liệu(HTML) 5 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL