PIC17C752-08SLASHCL datasheet(141/328 Pages) MICROCHIP

141 / 328 page

DS30289A-page 141

PIC17C7XX

15.2

MSSP I2C Operation

The MSSP module in I2C mode fully implements all

master and slave functions (including general call sup-

port) and provides interrupts on start and stop bits in

hardware to determine a free bus (multi-master func-

tion). The MSSP module implements the standard

mode speciﬁcations as well as 7-bit and 10-bit address-

ing. Appendix E: gives an overview of the I2C bus spec-

iﬁcation.

Refer to Application Note AN578,

"Use of the SSP

Module in the I 2C Multi-Master Environment."

A "glitch" ﬁlter is on the SCL and SDA pins when the pin

is an input. This ﬁlter operates in both the 100 kHz and

400 kHz modes. In the 100 kHz mode, when these pins

are an output, there is a slew rate control of the pin that

is independant of device frequency.

FIGURE 15-13: I2C SLAVE MODE BLOCK

DIAGRAM

Read

Write

SSPSR reg

Match detect

SSPADD reg

Start and

Stop bit detect

SSPBUF reg

Internal

data bus

Addr Match

Set, Reset

S, P bits

(SSPSTAT reg)

SCL

shift

clock

MSb

LSb

SDA

FIGURE 15-14: I2C MASTER MODE BLOCK

DIAGRAM

Two pins are used for data transfer. These are the SCL

pin, which is the clock, and the SDA pin, which is the

data. The SDA and SCL pins that are automatically

conﬁgured when the I2C mode is enabled. The SSP

module functions are enabled by setting SSP Enable

bit SSPEN (SSPCON1<5>).

The MSSP module has six registers for I2C operation.

These are the:

• SSP Control Register1 (SSPCON1)

• SSP Control Register2 (SSPCON2)

• SSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• SSP Shift Register (SSPSR) - Not directly acces-

sible

• SSP Address Register (SSPADD)

The SSPCON1 register allows control of the I2C oper-

ation. Four mode selection bits (SSPCON1<3:0>) allow

one of the following I2C modes to be selected:

•I2C Slave mode (7-bit address)

•I2C Slave mode (10-bit address)

•I2C Master mode, clock = OSC/4 (SSPADD +1)

Before selecting any I2C mode, the SCL and SDA pins

must be programmed to inputs by setting the appropri-

ate DDR bits. Selecting an I2C mode, by setting the

SSPEN bit, enables the SCL and SDA pins to be used

as the clock and data lines in I2C mode.

Read

Write

SSPSR reg

Match detect

SSPADD reg

Start and Stop bit

detect / generate

SSPBUF reg

Internal

data bus

Addr Match

Set/Clear S bit

Clear/Set P, bit

(SSPSTAT reg)

SCL

shift

clock

MSb

LSb

SDA

Baud Rate Generator

SSPADD<6:0>

and

and Set SSPIF

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