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PIC17C752-08/CL bảng dữ liệu(PDF) 25 Page - Microchip Technology |
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PIC17C752-08/CL bảng dữ liệu(HTML) 25 Page - Microchip Technology |
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25 / 328 page  © 1998 Microchip Technology Inc. DS30289A-page 25 PIC17C7XX TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS Register Address Power-on Reset Brown-out Reset MCLR Reset WDT Reset Wake-up from SLEEP through interrupt Unbanked INDF0 00h N.A. N.A. N.A. FSR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h 0000h 0000h PC + 1(2) PCLATH 03h 0000 0000 uuuu uuuu uuuu uuuu ALUSTA 04h 1111 xxxx 1111 uuuu 1111 uuuu T0STA 05h 0000 000- 0000 000- 0000 000- CPUSTA(3) 06h --11 11qq --11 qquu --uu qquu INTSTA 07h 0000 0000 0000 0000 uuuu uuuu(1) INDF1 08h N.A. N.A. N.A. FSR1 09h xxxx xxxx uuuu uuuu uuuu uuuu WREG 0Ah xxxx xxxx uuuu uuuu uuuu uuuu TMR0L 0Bh xxxx xxxx uuuu uuuu uuuu uuuu TMR0H 0Ch xxxx xxxx uuuu uuuu uuuu uuuu TBLPTRL 0Dh 0000 0000 0000 0000 uuuu uuuu TBLPTRH 0Eh 0000 0000 0000 0000 uuuu uuuu BSR 0Fh 0000 0000 0000 0000 uuuu uuuu Bank 0 PORTA (4,6) 10h 0-xx 11xx 0-uu 11uu u-uu uuuu DDRB 11h 1111 1111 1111 1111 uuuu uuuu PORTB (4) 12h xxxx xxxx uuuu uuuu uuuu uuuu RCSTA1 13h 0000 -00x 0000 -00u uuuu -uuu RCREG1 14h xxxx xxxx uuuu uuuu uuuu uuuu TXSTA1 15h 0000 --1x 0000 --1u uuuu --uu TXREG1 16h xxxx xxxx uuuu uuuu uuuu uuuu SPBRG1 17h 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition. Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt vector. 3: See Table 5-3 for reset value of specific condition. 4: This is the value that will be in the port output latch. 5: When the device is configured for microprocessor or externded microcontroller mode, the operation of this port does not rely on these registers 6: On any device reset, these pins are configured as inputs. |
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