PIC17C752-08SLASHP datasheet(53/320 Pages) MICROCHIP

53 / 320 page

Preliminary

DS30264A-page 53

PIC17C75X

7.8

Bank Select Register (BSR)

The BSR is used to switch between banks in the data

memory area (Figure 7-12). In the PIC17C752, and

PIC17C756 devices, the entire byte is implemented.

The lower nibble is used to select the peripheral regis-

ter bank. The upper nibble is used to select the general

purpose memory bank.

All the Special Function Registers (SFRs) are mapped

into the data memory space. In order to accommodate

the large number of registers, a banking scheme has

been used. A segment of the SFRs, from address 10h

to address 17h, is banked. The lower nibble of the bank

select register (BSR) selects the currently active

“peripheral bank.” Effort has been made to group the

peripheral registers of related functionality in one bank.

However, it will still be necessary to switch from bank

to bank in order to address all peripherals related to a

single task. To assist this, a MOVLB bank instruction

has been included in the instruction set.

The need for a large general purpose memory space

dictated a general purpose RAM banking scheme. The

upper nibble of the BSR selects the currently active

general purpose RAM bank. To assist this, a MOVLR

bank

instruction has been provided in the instruction

set.

If the currently selected bank is not implemented (such

as Bank 13), any read will read all '0's. Any write is

completed to the bit bucket and the ALU status bits will

be set/cleared as appropriate.

Note: Registers in Bank 15 in the Special Func-

tion Register area, are reserved for

Microchip use. Reading of registers in this

bank may cause random values to be read.

FIGURE 7-12: BSR OPERATION

74 3

10h

17h

BSR

• • •

20h

FFh

• • •

(1)

(2)

Bank 15

Bank 8

Bank 3

Bank 2

Bank 1

Bank 0

Bank 2

Bank 1

Bank 0

Bank 15

SFR

Banks

GPR

Banks

Address

Range

Note 1:

Only Banks 0 through 7 are implemented. Selection of an unimplemented bank is not recommended

Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random values to be read.

Bank 0 and Bank 1 are implemented for the PIC17C752, and Banks 0 through 3 are implemented for the PIC17C756.

Selection of an unimplemented bank is not recommended.

Bank 3

Bank 4

Bank 7

Bank 6

Bank 5

Bank 4

(Peripheral)

(RAM)

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