PIC16F872SLASHSP datasheet(18/160 Pages) MICROCHIP

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PIC16F872

DS30221A-page 18

Preliminary

2.2.2.7

PIR2 REGISTER

The PIR2 register contains the flag bits for the SSP bus

collision interrupt and the EEPROM write operation

interrupt.

PIR2 REGISTER (ADDRESS 0Dh)

Note:

Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

U-0

R/W-0

U-0

R/W-0

U-0

R/W-0

——

—

EEIF

BCLIF

—

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7

bit0

bit 7:

Unimplemented: Read as '0'

bit 6:

Reserved: Always maintain this bit clear

bit 5:

Unimplemented: Read as '0'

bit 4:

EEIF: EEPROM Write Operation Interrupt Flag bit

= The write operation completed (must be cleared in software)

= The write operation is not complete or has not been started

bit 3:

BCLIF: Bus Collision Interrupt Flag

= A bus collision has occurred in the SSP, when configured for I2C master mode

= No bus collision has occurred

bit 2-1:

Unimplemented: Read as '0'

bit 0:

Reserved: Always maintain this bit clear

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