DAC39J84IAAVR datasheet(92/146 Pages) TI

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DAC39J84

SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015

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7.5.1.50 config49 Register – Address: 0x31, Default: 0x0000

Figure 131. config49 Register Format

lockdet_ adj

pll_reset

pll_

pll_ena

pll_cp

ndivsync_ena

pll_n

memin_pll_lfvolt

Table 80. config49 Register Field Descriptions

Addr

Default

Bit

Name

Function

Name

(Hex)

Value

config49

0x31

15:13

lockdet_ adj

Adjusts the sensitivity of the DAC PLL lock detector; 4 settings from 000

000

to 011. The 011 setting has the widest lock detection window, tolerating

more jitter while reporting a lock. The 000 setting has a narrow window

and will indicate an unlocked state more often.

pll_reset

When set, the M divider, N divider and PFD are held reset.

pll_ ndivsync_ena When on, the SYSREF input is used to sync the N dividers of the PLL.

pll_ena

Enables the PLL output as the DAC clock when set; the clock provided at

the DACCLKP/N is used as the PLL reference clock. When cleared, the

FUSE

PLL is bypassed and the clock provided at the DACCLKP/N pins is used

controlled

as the DAC clock

9:8

pll_cp

Must be set to 00 for proper PLL operation

7:3

pll_n

Reference clock divider; divide by is N+1

00000

2:0

memin_pll_lfvolt

Indicates the loop filter voltage; 111 is max, 000 is min. When the PLL is

000

correctly programmed, this will read 011 or 100 for a centered loop filter

READ

voltage.

ONLY

7.5.1.51 config50 Register – Address: 0x32, Default: 0x0000

Figure 132. config50 Register Format

PLL_M

PLL_P

reserved

Table 81. config50 Register Field Descriptions

Addr

Default

Bit

Name

Function

Name

(Hex)

Value

config50

0x32

15:8

PLL_M

VCO feedback divider; divide by is M+1

00000000

7:4

PLL_P

VCO prescaler divider;

0000

0000 : div by 2

0001 : div by 3

0010 : div by 4

0011 : div by 5

0100 : div by 6

0101 : div by 7

0110 : div by 8

0111 : div by 9

1000 : div by 4

1001 : div by 6

1010 : div by 8

1011 : div by 10

1100 : div by 12

3:0

reserved

Reserved

0000

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