DAC39J84IAAVR datasheet(82/146 Pages) TI

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DAC39J84

SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015

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7.5.1.30 config29 Register – Address: 0x1D, Default: 0x0000

Figure 111. config29 Register Format

reserved

Table 60. config29 Register Field Descriptions

Addr

Default

Bit

Name

Function

Name

(Hex)

Value

config29

0x1D

15:8

reserved

0x00

7:0

reserved

0x00

7.5.1.31 config30 Register – Address: 0x1E, Default: 0x1111

Figure 112. config30 Register Format

syncsel_ qmoffsetab

syncsel_ qmoffsetcd

syncsel_ qmcorrab

syncsel_ qmcorrcd

Table 61. config30 Register Field Descriptions

Addr

Default

Bit

Name

Function

Name

(Hex)

Value

config30

0x1E

15:12

syncsel_ qmoffsetab

Select the sync for the QMCoffsetAB block. A ‘1’ in the selected bit

0x1

place allows the selected sync to pass to the block.

bit0 = auto-sync from SIF register write

bit1 = sysref

bit2 = sync_out from JESD

bit3 = sif_sync

11:8

syncsel_ qmoffsetcd

Select the sync for the QMCoffsetCD block. A ‘1’ in the selected bit

0x1

place allows the selected sync to pass to the block.

bit0 = auto-sync from SIF register write

bit1 = sysref

bit2 = sync_out from JESD

bit3 = sif_sync

7:4

syncsel_ qmcorrab

Select the sync for the QMCcorrAB block. A ‘1’ in the selected bit place

0x1

allows the selected sync to pass to the block.

bit0 = auto-sync from SIF register write

bit1 = sysref

bit2 = sync_out from JESD

bit3 = sif_sync

3:0

syncsel_ qmcorrcd

Select the sync for the QMCcorrCD block. A ‘1’ in the selected bit place

0x1

allows the selected sync to pass to the block.

bit0 = auto-sync from SIF register write

bit1 = sysref

bit2 = sync_out from JESD

bit3 = sif_sync

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