DAC39J84IAAVR datasheet(53/146 Pages) TI

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DAC39J84

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SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015

Table 22. ws_tuning Chain

FIELD

DESCRIPTION

HEAD (STARTING FROM THE MSB OF CHAIN)

RETIME

No function.

RECEIVER (FOR EACH LANE 0,1,2,3)

PATTERRTHR[2:0]

Resync error threshold.

PATT TIMER

PRBS Timer.

RXDSEL[3:0]

Status select.

ENCOR

Enable clear-on-read for error counter.

EQZERO[4:0]

EQZ OVRi Equalizer zero.

EQZ OVR

Equalizer zero over-ride.

EQLEVEL[15:0]

EQ OVRi Equalizer gain observe or set.

EQ OVR

Equalizer over-ride.

EQBOOST[1:0]

Equalizer gain boost.

RXASEL[2:0]

Selects amux output.

TAIL (ENDING WITH THE LSB OF CHAIN)

ASEL[3:0]

Selects amux output.

USR PATT[19:0]

User-defined test pattern.

RETIME

No function.

CHAIN LENGTH = 174 BITS

Table 23. ws_char Chain

FIELD

DESCRIPTION

HEAD (STARTING FROM THE MSB OF CHAIN)

RETIME

No function.

RECEIVER (FOR EACH LANE 0,1,2,3)

TESTFAIL

Test failure (sticky).

ECOUNT[11:0]

Error counter.

ESWORD[7:0]

Eye scan word masking.

ES[3:0]

Eye scan.

ESPO[6:0]

Eye scan phase offset.

ES BIT SELECT[4:0]

Eye scan compare bit select.

ESVO[5:0]

Eye scan voltage offset.

ESVO OVR

Eye scan voltage offset override.

ESLEN[1:0]

Eye scan run length.

ESRUN

Eye scan run.

ESDONE

Eye scan done.

TAIL (ENDING WITH THE LSB OF CHAIN)

RETIME

No function.

CHAIN LENGTH = 194 BITS

7.3.20 Error Counter

All receive channels include a 12-bit counter for accumulating pattern verification errors. This counter is

accessible via the ECOUNT IEEE1500 Char field. It is an essential part of the eye scan capability (see next

section), though can be used independently of this..

The counter increments once for every cycle that the TESTFAIL bit is detected. The counter will not increment

when at its maximum value (i.e., all 1s). When an IEEE1500 capture is performed, the count value is loaded into

the ECOUNT scan elements (so that it can be scanned out), and the counter is then reset, provided ENCOR is

set high.

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