MAX532BCSLASHD datasheet(4/16 Pages) MAXIM

4 / 16 page

Dual, Serial-Input,

Voltage-Output, 12-Bit MDAC

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL = 2kΩ, CL = 100pF,

VOUT_ connected to RFB_, TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SYMBOL

VREF = 100mVp-p sine wave;

DAC latch loaded with all 1s

1.0

MHz

VREF = 20Vp-p 10kHz sine wave;

DAC latch loaded with all 0s

-77

Full-Power Bandwidth

125

kHz

THD

Total Harmonic Distortion

-90

Output Noise Voltage

0.1Hz to 10Hz

µVRMS

Digital Crosstalk

DACA code all 1s, DACB code transition from all 0s to all 1s

nV-s

Digital Feedthrough

CS = 1; transitions on SCLK, LDAC, DIN

1.1

nV-s

PARAMETER

tCL

CONDITIONS

MIN

TYP

MAX

SCLK Pulse Width Low

UNITS

SYMBOL

fCLK

tCH

tDS

tCSS1

CS Rise to SCLK Rise Setup Time

SCLK Clock Frequency

tCSS0

CS Fall to SCLK Rise Setup Time

6.25

MHz

tDH

DIN to SCLK Rise Hold Time

SCLK Pulse Width High

Multiplying Feedthrough

Error

Unity-Gain Small-Signal

Bandwidth

VREF = 20Vp-p sine wave;

DAC latch loaded with all 1s

VREF = 6VRMS, 1kHz sine wave;

DAC latch loaded with all 1s

Note 1: Static performance tested at VDD = +15V, VSS = -15V. Performance over supplies guaranteed by PSR test.

Note 2: Guaranteed by design. Not subject to production testing.

Note 3: Open-drain output.

TIMING CHARACTERISTICS

(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V) (Notes 4, 5)

tCSH0

SCLK Fall to

CS Fall Hold Time

tCSH1

SCLK Rise to

CS Rise Hold Time

tCSW

CS Pulse Width High

120

tDO

SCLK Fall to DOUT Valid (Note 6)

CL = 20pF, RPULL-UP = 1kΩ to 5V

200

tDV

CS Fall to DOUT Enable (Note 7)

CL = 20pF, RPULL-UP = 1kΩ to 5V

100

tTR

CS Rise to DOUT Disable (Note 7)

CL = 20pF, RPULL-UP = 1kΩ to 5V

tLDAC

LDAC Pulse Width Low

tLDACS

CS Rise to LDAC Fall Setup Time

100

DIN to SCLK Rise Setup Time

Note 4: All input signals are specified with tR = tF ≤ 5ns. Logic input swing is 0V to 5V.

Note 5: See Figure 1.

Note 6: Timing is for SCLK fall to DOUT fall to 0.8V, or for SCLK fall to DOUT rise to 2.4V. Additional time must be added for any

larger passive RC pull-up delay.

Note 7: DOUT enable: DOUT falls to 4.5V from 5.0V. DOUT disable: DOUT rises to 0.5V from 0V.

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