MAX532BCSLASHD datasheet(11/16 Pages) MAXIM

11 / 16 page

With the values of tRC given in Table 1, tCSS0 is always

given by tDV + tDS. For different values of R or C, tRC

must be calculated to determine tCSS0.

Additionally, the maximum clock frequency is limited to

fCLK (max) =

————————————— .

2 x (tDO + tRC -15ns + tDS)

For example, with tRC = 15ns (5V ±10% supply with

Ω pull-up), the maximum clock frequency is 2MHz.

Digital-to-Analog Section

Figure 8 shows a simplified circuit diagram for one of

the DACs and the output amplifier.

A segmented scheme is used to improve linearity,

whereby the two MSBs of the 12-bit data word are

decoded to drive the three switches, SA, SB, and SC.

The remaining ten bits drive the switches S0 through S9

in a standard R-2R ladder configuration.

Each of the switches, SA, SB, and SC, steers 1/4 of the

total reference current with the remaining 1/4 passing

through the R-2R section.

The output amplifier and feedback resistor perform the

current-to-voltage conversion, giving the following:

VOUT_ = -D x VREF_,

where _ denotes A or B, and D is the fractional representa-

tion of the digital word. (D can be set from 0 to 4095/4096.)

Dual, Serial-Input,

Voltage-Output, 12-Bit MDAC

______________________________________________________________________________________

VPULL-UP (V)

C (pF)

RP (kΩ)tRC (ns)

4.5

100

4.5

150

114

11.4

100

11.4

150

106

13.5

100

13.5

150

Table 1. tRC Delay Times

R/2

RFB_

VOUT_

AGND_

SHOWN FOR ALL 1s ON DAC

VREF_

Figure 8. Simplified D/A Circuit Diagram

DACA

AGNDA

VSS

DGND

RFBA

VOUTA

VOUT

VIN

-12V to -15V

VDD

VREFA

+12V to +15V

MAX532

Figure 9. Unipolar Binary Operation

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