Low-Voltage, Silicon RF Power

Amplifier/Predriver

6

_______________________________________________________________________________________

__________Applications Information

Output Matching

The optimum internal load impedance seen by RFOUT

is approximately 15

Ω. This on-chip low drive imped-

ance provides maximum power transfer and best effi-

ciency under low (3V) supply conditions where the

voltage-swing headroom is limited. For example, driv-

ing an output power of 21.3dBm (135mW) into 50

Ω

translates to a 7.35Vp-p swing at the output. An RF

amplifier would require at least a 4.5V supply to drive a

50

Ω load directly. However, driving 21.3dBm into 15Ω

translates to 4.02Vp-p. The MAX2430 can achieve a

voltage swing of 4.02Vp-p or 2.01Vp from a 3V supply

voltage without saturating the output transistor.

Figure 1 shows the MAX2430 configured for 800MHz to

1000MHz operation. The output matching circuitry con-

verts the desired 50

Ω load impedance to the 15Ω opti-

mal load seen by the output transistor’s collector. This

configuration uses a low-loss, controlled-Q inductor net-

work. Starting from the RFOUT pin, this network consists

of a series L (which includes the 5nH package parasitic

inductance), series C, and shunt C. The design equa-

tions for this network are as follows:

R1 = Output resistance as seen by the

collector ~15

Ω

The controlled-Q inductor network requires that

. Choose Q and com-

pute matching components as given below:

where

ω equals the center frequency in radians/second.

Recommended starting values for L1 and L2 are given

in Table 1.

Let

A

R x R1

R1

X

Q x R1

X

X

A

X

R x R1 / A

L1 = X /

- 5nH of package

inductance

C

=

1

X

C

=

1

X

L

2

L

Co

L

Csh

L

L

O

Co

SH

Csh

=−

()

=

=−

=

ω

ω

ω

R / R1

1

L

−

()

MAX2430

OUTPUT

BIAS

GAIN

50

Ω

˜50Ω

GND2

GND3

VCC1

1nF

1nF

2.2nF

VCC2

BIAS

GND4

RFOUT

THREE-ELEMENT

MATCHING NETWORK

DESIRED FREQUENCY BETWEEN 800MHz AND 1000MHz.

MAX2430IEE (PwrQSOP) UNDERSIDE METAL SLUG MUST

BE SOLDERED TO PCB GROUND PLANE.

L2 = 8nH FOR NARROW SO PACKAGE (MAX2430ISE)

L2 = 12nH FOR PwrQSOP PACKAGE (MAX2430IEE)

*

9

5nH

47nH

470

Ω

L2*

RF OUTPUT

L1

8nH

SHDN

ON

OFF

GND1

RFIN

1nF

DRIVER

MASTER

BIAS

˜

15

Ω

RF INPUT

Figure 1. Typical Application Circuit

L1(nH)

400 to 600*

22

800 to 1000

8

Table 1. Recommended L1 and L2 Starting

Values

*Not characterized

f =

ω / 2π

(MHz)

600 to 800*

15

MAX2430ISE

L2(nH)

8

12

8

MAX2430IEE

L2(nH)

12

18

12