Low-Voltage, Silicon RF Power

Amplifier/Predriver

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5

_____________________Pin Description

NAME

FUNCTION

1, 15,

16

GND3

Driver Stage Ground. Connect directly to

ground plane.

2

SHDN

Shutdown Input (TTL/CMOS)

PIN

3, 5

GND2

Input Stage Ground. Connect directly to

ground plane.

4

RFIN

RF Input. Internally matched to 50

Ω.

Requires series DC-blocking capacitor.

9

RFOUT

Output Transistor. Open Collector.

8

VCC2

Driver Stage Output. Connect to supply

through inductor (see

Applications

Information).

7

VCC1

Bias Circuitry Supply. Connect to supply.

Bypass with 1000pF capacitor.

6

GND1

Bias Circuitry Ground. Connect directly to

ground plane.

11–14

GND4

Output Stage Ground. Connect directly to

ground plane.

10

BIAS

Output Stage Bias Pin. Connect capacitor

to GND to control start-up power enve-

lope. Drive directly for power control (see

Applications Information).

Detailed Description

The MAX2430 consists of a large power output transis-

tor driven by a capacitively coupled driver stage (see

Functional Diagram). The driver and front-end gain

stages are DC-connected and biased on-chip from the

master bias cell. The master bias cell also controls the

output stage bias circuit. The input impedance at the

RFIN pin is internally matched to 50

Ω, while the output

stage must be tuned and filtered externally for any nar-

row-band frequency range of interest between 800MHz

and 1000MHz.

The driver amplifier requires an external inductor at the

VCC2 pin to provide DC bias and proper matching to

the output stage. This inductor’s value depends on the

package type and frequency range of operation; typi-

cally it will vary between 5nH and 22nH.

The output transistor at the RFOUT pin requires an

external RF choke inductor connected to the supply for

DC bias, and a matching network to transform the

desired external load impedance to the optimal internal

load impedance of approximately 15

Ω.

The MAX2430 includes a unique shutdown feature. The

TTL/CMOS-compatible SHDN input allows the device to

be shut down completely without the use of any exter-

nal components. Also, the RF output power envelope

ramp time can be programmed with a single external

capacitor connected between the BIAS pin and

ground. Pulling the shutdown pin (SHDN) high powers

on the master bias circuit, which in turn charges the

external capacitor tied to the BIAS pin using a con-

trolled current. The voltage at BIAS controls the output

power level, which ramps until the BIAS pin is internally

clamped to approximately 2.2V. The envelope ramp-

down time is controlled in a similar manner when the

SHDN pin is pulled low.

Variable output power control over a 15dB range is also

possible by forcing the voltage on the BIAS pin exter-

nally from 0.6V to 2.4V.

During the on state (SHDN = high), the power-supply

bias current is typically 52mA with no RF applied to the

input. During the off state (SHDN = low), the supply

current is typically reduced to less than 1µA.

Note:

MAX2430IEE (PwrQSOP package) underside metal slug

must be soldered to PCB ground plane.