24

PALCE20V8 Family

POWER-UP RESET

The PALCE20V8 has been designed with the capability to reset during system power-up.

Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH

independent of the logic polarity. This feature provides extra flexibility to the designer and is

especially valuable in simplifying state machine initialization. A timing diagram and parameter

table are shown below. Due to the synchronous operation of the power-up reset and the wide

power-up reset. These conditions are:

x

x

Following reset, the clock input must not be driven from LOW to HIGH until all applicable input

and feedback setup times are met.

Parameter Symbol

Parameter Descriptions

Min

Max

Unit

Power-Up Reset Time

1000

ns

Input or Feedback Setup Time

See Switching Characteristics

Clock Width LOW

4 V

Power

Registered

Output

Clock

16491E-15

Figure 2. Power-Up Reset Waveform