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ISPMACH4ACPLDFAMILY bảng dữ liệu(PDF) 38 Page - Lattice Semiconductor |
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ISPMACH4ACPLDFAMILY bảng dữ liệu(HTML) 38 Page - Lattice Semiconductor |
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38 / 62 page ![]() 38 ispMACH 4A Family ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 -5 -55 -6 -65 -7 -10 -12 -14 Unit Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Combinatorial Delay: tPDi Internal combinatorial propagation delay 3.5 4.0 4.3 4.5 5.0 7.0 9.0 11.0 ns tPD Combinatorial propagation delay 5.0 5.5 6.0 6.5 7.5 10.0 12.0 14.0 ns Registered Delays: tSS Synchronous clock setup time, D-type register 3.0 3.5 3.5 3.5 5.0 5.5 7.0 10.0 ns tSST Synchronous clock setup time, T-type register 4.0 4.0 4.0 4.0 6.0 6.5 8.0 11.0 ns tSA Asynchronous clock setup time, D-type register 2.5 2.5 2.5 3.0 3.5 4.0 5.0 8.0 ns tSAT Asynchronous clock setup time, T-type register 3.0 3.0 3.0 3.5 4.5 5.0 6.0 9.0 ns tHS Synchronous clock hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns tHA Asynchronous clock hold time 2.5 2.5 2.5 3.0 3.5 4.0 5.0 8.0 ns tCOSi Synchronous clock to internal output 2.5 2.5 2.8 3.0 3.0 3.0 3.5 3.5 ns tCOS Synchronous clock to output 4.0 4.0 4.5 5.0 5.5 6.0 6.5 6.5 ns tCOAi Asynchronous clock to internal output 5.0 5.0 5.0 5.0 6.0 8.0 10.0 12.0 ns tCOA Asynchronous clock to output 6.5 6.5 6.8 7.0 8.5 11.0 13.0 15.0 ns Latched Delays: tSSL Synchronous latch setup time 4.0 4.0 4.0 4.5 6.0 7.0 8.0 10.0 ns tSAL Asynchronous latch setup time 3.0 3.0 3.5 3.5 4.0 4.0 5.0 8.0 ns tHSL Synchronous latch hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns tHAL Asynchronous latch hold time 3.0 3.0 3.5 3.5 4.0 4.0 5.0 8.0 ns tPDLi Transparent latch to internal output 5.5 5.5 5.8 6.0 7.5 9.0 11.0 12.0 ns tPDL Propagation delay through transparent latch to output 7.0 7.0 7.5 8.0 10.0 12.0 14.0 15.0 ns tGOSi Synchronous gate to internal output 3.0 3.0 3.0 3.0 3.5 4.5 7.0 8.0 ns tGOS Synchronous gate to output 4.5 4.5 4.8 5.0 6.0 7.5 10.0 11.0 ns tGOAi Asynchronous gate to internal output 6.0 6.0 6.0 6.0 8.5 10.0 13.0 15.0 ns tGOA Asynchronous gate to output 7.5 7.5 7.8 8.0 11.0 13.0 16.0 18.0 ns Input Register Delays: tSIRS Input register setup time 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 ns tHIRS Input register hold time 2.5 2.5 3.0 3.0 3.0 3.0 3.0 4.0 ns tICOSi Input register clock to internal feedback 3.0 3.0 3.0 3.0 3.5 4.5 6.0 6.0 ns Input Latch Delays: tSIL Input latch setup time 1.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 ns tHIL Input latch hold time 2.5 2.5 2.5 3.0 3.0 3.0 3.0 4.0 ns tIGOSi Input latch gate to internal feedback 3.5 3.5 3.8 4.0 4.0 4.0 4.0 5.0 ns tPDILi Transparent input latch to internal feedback 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 ns |
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