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ISPMACH4ACPLDFAMILY bảng dữ liệu(PDF) 39 Page - Lattice Semiconductor

tên linh kiện ISPMACH4ACPLDFAMILY
Giải thích chi tiết về linh kiện  High Performance E 2 CMOS In-System Programmable Logic
PDF  62 Pages
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nhà sản xuất  LATTICE [Lattice Semiconductor]
Trang chủ  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ISPMACH4ACPLDFAMILY bảng dữ liệu(HTML) 39 Page - Lattice Semiconductor

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ispMACH 4A Family
39
Input Register Delays with ZHT Option:
tSIRZ Input register setup time - ZHT
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
ns
tHIRZ Input register hold time - ZHT
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
Input Latch Delays with ZHT Option:
tSILZ Input latch setup time - ZHT
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
ns
tHILZ Input latch hold time - ZHT
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
tPDIL
Zi
Transparent input latch to internal
feedback - ZHT
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
ns
Output Delays:
tBUF
Output buffer delay
1.5
1.5
1.8
2.0
2.5
3.0
3.0
3.0
ns
tSLW
Slow slew rate delay adder
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns
tEA
Output enable time
7.5
7.5
8.5
8.5
9.5
10.0
12.0
15.0
ns
tER
Output disable time
7.5
7.5
8.5
8.5
9.5
10.0
12.0
15.0
ns
Power Delay:
tPL
Power-down mode delay adder
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns
Reset and Preset Delays:
tSRi
Asynchronous reset or preset to internal
register output
7.5
7.7
8.0
8.0
9.5
11.0
13.0
16.0
ns
tSR
Asynchronous reset or preset to register
output
9.0
9.2
10.0
10.0
12.0
14.0
16.0
19.0
ns
tSRR
Asynchronous reset and preset register
recovery time
7.0
7.0
7.5
7.5
8.0
8.0
10.0
15.0
ns
tSRW Asynchronous reset or preset width
7.0
7.0
8.0
8.0
10.0
10.0
12.0
15.0
ns
Clock/LE Width:
tWLS
Global clock width low
2.0
2.0
2.5
2.5
3.0
4.0
5.0
6.0
ns
tWHS Global clock width high
2.0
2.0
2.5
2.5
3.0
4.0
5.0
6.0
ns
tWLA Product term clock width low
3.0
3.0
3.5
3.5
4.0
5.0
8.0
9.0
ns
tWHA Product term clock width high
3.0
3.0
3.5
3.5
4.0
5.0
8.0
9.0
ns
tGWS
Global gate width low (for low
transparent) or high (for high
transparent)
4.0
4.0
4.5
4.5
5.0
5.0
6.0
6.0
ns
tGWA
Product term gate width low (for low
transparent) or high (for high
transparent)
4.0
4.0
4.5
4.5
5.0
5.0
6.0
9.0
ns
tWIRL Input register clock width low
3.0
3.0
3.5
3.5
4.0
5.0
6.0
6.0
ns
tWIRH Input register clock width high
3.0
3.0
3.5
3.5
4.0
5.0
6.0
6.0
ns
tWIL
Input latch gate width
4.0
4.0
4.5
4.5
5.0
5.0
6.0
6.0
ns
ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-5
-55
-6
-65
-7
-10
-12
-14
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max



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