UPD70F3003A datasheet(19/44 Pages) NEC

19 / 44 page

µPD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

(1) Clock timing

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

X1 input cycle

<1>

tCYX

Direct mode

Note 1

PLL mode

200

Note 1

151

Note 1

(PLL lock status)

X1 input width, high

<2>

tWXH

Direct mode

PLL mode

X1 input width, low

<3>

tWXL

Direct mode

PLL mode

X1 input rise time

<4>

tXR

Direct mode

PLL mode

X1 input fall time

<5>

tXF

Direct mode

PLL mode

CPU operating frequency

—

Note 2

MHz

CLKOUT output cycle

<6>

tCYK

Note 3

CLKOUT width, high

<7>

tWKH

0.5 T – 5

CLKOUT width, low

<8>

tWKL

0.5 T – 5

CLKOUT rise time

<9>

tXR

CLKOUT fall time

<10>

tXF

↓→ CLKOUT delay time

<11>

tDXK

Direct mode

Notes 1. When A/D converter used: 100 ns

When A/D converter not used: 250 ns

2. When A/D converter used: 5 MHz

When A/D converter not used: 2 MHz

3. When A/D converter used: 200 ns

When A/D converter not used: 500 ns

Remark

T = tCYK

<1>

<2>

<4>

<11>

<5>

<6>

<7>

<9>

<10>

<8>

<3>

X1 (input)

CLKOUT (output)

<11>

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