AN3114 datasheet(21/43 Pages) STMICROELECTRONICS

21 / 43 page

AN3114

Integrated LCD controller

Doc ID 16829 Rev 3

21/43

Generation of the LCD voltage levels

The internal booster includes two resistive networks, one with low value resistors (RL) and

one with high value resistor (RH) which are respectively used to increase the current during

transitions and to reduce consumption in static state (see Figure 12).

●

The EN switch follows the rules below:

–

When the LCDEN bit in the LCD_CR3 register is set, the EN switch is closed.

–

When clearing the LCDEN bit in the LCD_CR3, the EN switch is open at the end

of the even frame in order to avoid a medium voltage level different from 0 during

the frame.

The PON[2:0] (Pulse ON duration) bits in the LCD_CR2 register configure the time during

which RL is enabled (see Figure 10 and Figure 11) through a HD (high drive) when the

levels of common and segment lines change. A short drive time decreases power

consumption, but displays with high internal resistance may need a longer drive time to

achieve a satisfactory contrast.

The RL divider can be always switched on using the HD bit in the LCD_CR2 register.

●

The RL divider is enabled when the HD signal is set only for a short period of time when

the levels of common and segment lines change. This time can be programmed

through the Pulse ON bits (PON[2:0]) of the LCD_CR2 register. The HD signal follows

the rules described below:

–

If the HD bit and the PON[2:0] bits in the LCD_CR2 are reset, then the HD signal

is open.

–

If the HD bit in the LCD_CR2 register is reset and the PON[2:0] bits in the

LCD_CR2 are different from 00, then the HD signal is closed during the number of

pulses defined in the PON[2:0] bits.

–

If the HD bit in the LCD_CR2 register is 1, then the HD signal is always closed.

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