UPD703003A datasheet(31/40 Pages) NEC

31 / 40 page

µPD703003A, 703004A, 703025A

Data Sheet U13188EJ4V0DS00

(9) CSI timing (1/2)

(a) Master mode

(i)

Timing of CSI0 to CSI2

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

SCKn cycle

<67> tCYSK1

Output

160

120

SCKn high-level width

<68> tWSKH1

Output

0.5tCYSK1 – 20

SCKn low-level width

<69> tWSKL1

Output

0.5tCYSK1 – 20

SIn setup time (to SCKn

↑)

<70> tSSISK1

SIn hold time (from SCKn

↑)

<71> tHSKSI1

SOn output delay time (from SCKn

↓) <72> tDSKSO1

SOn output hold time (from SCKn

↑) <73> tHSKSO1

0.5tCYSK1 – 5

Remark

n = 0 to 2

(ii) Timing of CSI3

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

SCK3 cycle

<67> tCYSK3

Output

RL = 1.5 k

Ω

500

SCK3 high-level width

<68> tWSKH3

Output

CL = 50 pF

0.5tCYSK3 – 70

SCK3 low-level width

<69> tWSKL3

Output

0.5tCYSK3 – 70

SI3 setup time (to SCK3

↑)

<70> tSSISK3

100

SI3 hold time (from SCK3

↑)

<71> tHSKSI3

SO3 output delay time (from SCK3

↓) <72> tDSKSO3

RL = 1.5 k

Ω

150

SO3 output hold time (from SCK3

↑) <73> tHSKSO3

CL = 50 pF

0.5tCYSK3 – 5

Remark

RL and CL are the load resistance and load capacitance of the SCK3 and SO3 output lines.

(b) Slave mode

(i)

Timing of CSI0 to CSI2

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

SCKn cycle

<67> tCYSK2

Input

160

120

SCKn high-level width

<68> tWSKH2

Input

SCKn low-level width

<69> tWSKL2

Input

SIn setup time (to SCKn

↑)

<70> tSSISK2

SIn hold time (from SCKn

↑)

<71> tHSKSI2

SOn output delay time (from SCKn

↓) <72> tDSKSO2

SOn output hold time (from SCKn

↑) <73> tHSKSO2

tWSKH2

Remark

n = 0 to 2

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