AN2476 datasheet(18/49 Pages) STMICROELECTRONICS

18 / 49 page

Power supply and clocks

AN2476

18/49

Note:

This latency does not occur if the software fetches from SRAM when it restarts. Any access

to Flash will be performed correctly, but will result in wait states being inserted if the Flash is

not ready.

The Flash must be configured all the above control parameters, even if SRAM is used to

fetch parts of the software.

1.8.5

STOP mode

In this mode CK_SYS is stopped. This means that the CPU and all the peripherals clocked

by CK_SYS or derived clocks are disabled. As a result, the AHB and APB peripherals are

not clocked, so the digital part of the MCU consumes no power other than the leakage

current due to the process technology.

In STOP mode, all the registers and SRAM contents are preserved, the PLL and clock

configuration can remain unchanged.

STOP mode entry procedure

Use the following procedure to enter STOP mode:

First select STOP Mode by programming the LPMC[1:0] bits in the MRCC_PWRCTRL

Program the LP_PARAM bits in the MRCC_PWRCTRL register to enable or disable

some peripherals in STOP mode

Execute the Low Power Bit Writing Sequence as described in Section 1.8.1: Low power

bit writing sequence on page 14.

Table 2.

WFI mode functionality

Control

bits

Functionality in WFI mode

Wake-up

resources

Wake-

latency

due to:

Clock

config.

state after

wake-up

All

Main

VREG

On On

Off (in

non Burst

mode)

Yes

Yes if

enabled

All

Yes

Flash

Unchanged

Yes

On On

(enabled

or low

power

mode)

latency

Yes

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