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AN2009 bảng dữ liệu(PDF) 16 Page - STMicroelectronics |
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AN2009 bảng dữ liệu(HTML) 16 Page - STMicroelectronics |
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16 / 39 page ![]() 16/39 PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7MC Figure 11. Oscilloscope waveforms: Current Mode Note: In speed regulation, the 12-bit timer PWM duty cycle only has to have the right value to start the motor. Once the target speed is reached, the PWM duty cycle will be adjusted auto- matically by the ST7MC. 4.2.2 PWM signal register setting in Current mode In current mode, a combination of an internal clock and the output of the current comparator is used to set the PWM signal, the registers described below are the ones used to set the fre- quency and the minimum OFF time if needed from the PWM signal for the internal clock. PRESCALER & SAMPLING REGISTER (MPRSR) Read/Write Reset Value: 0000 0000 (00h) Bits 7:4 = SA[3:0]: Sampling Ratio. These bits contain the sampling ratio value for current mode. This sets the frequency of the PWM according to the following table 7 6 5 4 3 2 1 0 SA3 SA2 SA1 SA0 X X X X 1. Current in Phase A 2. Signal on High Side Triple Half Bridge Configuration 4. Current Feedback 3. Current Regulation Switch of Phase A on Signal through PWM Compare U filtered |
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