AN1709 datasheet(20/38 Pages) STMICROELECTRONICS

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EMC DESIGN GUIDE FOR ST MICROCONTROLLERS

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the

VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles).

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software

to shut down safely before the LVD resets the microcontroller. (See Figure 13.).

The interrupt on the rising edge is used to inform the application that the VDD warning state is

over.

If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay

of the Microcontroller), no AVD interrupt will be generated when VIT+(AVD) is reached.

If trv is greater than 256 or 4096 cycles then:

– If the AVD interrupt is enabled before the VIT+(AVD) threshold is reached, then 2 AVD inter-

rupts will be received: the first when the AVDIE bit is set, and the second when the threshold

is reached.

– If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached then only one AVD

interrupt will occur.

Figure 13. Using the AVD to Monitor VDD

VDD

VIT+(AVD)

VIT-(AVD)

AVDF bit

RESET VALUE

IF AVDIE bit = 1

Vhyst

AVD INTERRUPT

REQUEST

INTERRUPT PROCESS

VIT+(LVD)

VIT-(LVD)

LVD RESET

Early Warning Interrupt

(Power has dropped, MCU not

not yet in reset)

trv VOLTAGE RISE TIME

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